Double diffused vertical JFET

Details Double diffused vertical JFET Double diffused vertical JFET

2005-03-01

2005-03-01

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S135000

Reexamination Certificate

active

06861678

ABSTRACT:
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a body region above the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

REFERENCES:
patent: 6008520 (1999-12-01), Darwish et al.
patent: 6084254 (2000-07-01), Kim
Pending U.S. Application No. 10/614,840 (TI-35193) Howard et al. “Implant-Controlled-Channel Vertical JFET”.
Pending U.S. Application No. 10/678,028 (TI-33654), Pendharker et all “A Low Noise Vertical Variable Gate Control Voltage JFET Device in a BICMOS Process & Methods to Build this Device”.

Affiliated with

Also associated with

Rating

Double diffused vertical JFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Double diffused vertical JFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double diffused vertical JFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3451106