Double diffused mosfet with potential biases

Details Double diffused mosfet with potential biases Double diffused mosfet with potential biases

1987-12-14

1989-11-28

Mintel, William

357 34, 357 54, 357 234, 357 238, 357 49, H01L 2702

Patent

active

048841161

ABSTRACT:
First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with eacth other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential. In this way, it is possible to improve the yield voltage characteristics between the first semiconductor region, which does not form any element, and the back gate region. The insulating region which electrically isolates the first and second semiconductor regions from each other, is formed by bonding together first and second silicon oxide films on surface of the first and second single crystal silicon substrates. Therefore, the process of manufacture is simplified.

REFERENCES:
patent: 3598664 (1971-08-01), Kirby
patent: 3817799 (1974-06-01), Schutze et al.
patent: 4241359 (1980-12-01), Izumi et al.
patent: 4523213 (1985-05-01), Konaka et al.
patent: 4786952 (1988-11-01), MacIver et al.
Augusta et al., "Monolithic Integrated Semiconductor Structure with Multilevel Conductive Interconnection Planes", IBM Technical Disclosure Bulletin, vol. 9, No. 7, Dec. 1966, pp. 951-952.
Brock et al., "Fusion of Silicon Wafers", IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, pp. 3405-3406.

Affiliated with

Also associated with

Rating

Double diffused mosfet with potential biases does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Double diffused mosfet with potential biases, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double diffused mosfet with potential biases will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-585298