Double-diffused, insulated-gate, field effect transistor

Details Double-diffused, insulated-gate, field effect transistor Double-diffused, insulated-gate, field effect transistor

1988-04-28

1989-11-28

James, Andrew J.

357 238, 357 13, H01L 2978, H01L 2990

Patent

active

048841137

ABSTRACT:
A double-diffused insulated-gate field effect transistor is disclosed having impurity regions each acting as a channel base region and depletion layer preventing regions having a high concentration impurity and being of a conductivity type opposite to that of the base region. With the transistor in the ON state a depletion layer is confined within the depletion layer preventing region, preventing an increase in ON resistance in a narrow region between the channel base regions. The concentration and diffusion depth of the depletion layer preventing region are such that, due to the presence of the depletion layer preventing region, the reverse bias voltage between the channel base region and a drain region causes no avalanche breakdown between the channel base region and the drain region.

REFERENCES:
patent: 4233617 (1980-11-01), Klaassen et al.
patent: 4300150 (1981-11-01), Colak
patent: 4376286 (1983-03-01), Lidow et al.

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