Double-diffused drain CMOS process using a counterdoping techniq

Details Double-diffused drain CMOS process using a counterdoping techniq Double-diffused drain CMOS process using a counterdoping techniq

1989-06-27

1990-09-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 45, 437953, H01L 21336

Patent

active

049563114

ABSTRACT:
The present process comprises the use of a blanket phosphorus (n-) implant coupled with a masked boron (P+) implant to permit the elimination of the conventional N+ implant and the LDD masks. The use of the blanket n- implant and the masked p+ implant allows production of an n- drain region which reduces hot-electron-induced degradation and a low concentration S/D region which is subsequently more easily counterdoped by a high concentration implant. A shallow blanket n+ implant is included prior to the P+ mask step to prevent contact resistance problems. Thereafter in the process of this invention, a salicide is formed at the sources and drains to produce a low sheet resistance in the contacts of the n-channel devices, notwithstanding the absence of the conventional thick n+ layer.

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