Double differential summing amplifier with four independent inpu

Details Double differential summing amplifier with four independent inpu Double differential summing amplifier with four independent inpu

1987-06-26

1988-10-25

Laroche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

330 69, 330253, H03F 316

Patent

active

047806303

ABSTRACT:
A double differential summing amplifier circuit with four independent inputs, having two equipotential supply lines L1 and L2 raised respectively to potentials -V and +V; four MOS amplifier transistors M1, M2, M3 and M4, the gates of which constitute the inputs e1, e2, e3 and e4 of the circuit and which are respectively connected to sources supplying the voltages to be amplified of values Ve1, Ve2, V33 and Ve4, the drains D1, D2, D3 and D4 of these transistors being connected pairwise, namely D1 and D3 of transistors M1 and M3, on the one hand, for constituting the first output of the circuit on which is collected the amplified voltage Vs1, and D2 and D4 of transistors M2 and M4, on the other hand, for constituting the second output of the circuit on which is collected the amplified voltage Vs2; four load resistors M5, M6, M7 and M8 respectively connecting the drains D1, D2, D3 and D4 of transistors M1, M2, M3 and M4 to equipotential line L1; an MOS transistor M9 functioning as a current generator, whose drain D9 is connected to the common point of the four sources S1, S2, S3 and S4 of transistors M1, M2, M3 and M4, the source S9 of which is connected to equipotential line L2 and whose gate g9 is connected to a polarizing voltage source Upol3.

REFERENCES:
patent: 3956643 (1976-05-01), Hite
patent: 4081758 (1978-03-01), Steckler
patent: 4460874 (1984-07-01), Haque

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