Double data rate synchronous dynamic random access memory...

Details Double data rate synchronous dynamic random access memory... Double data rate synchronous dynamic random access memory...

2006-05-02

2006-05-02

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189050

Reexamination Certificate

active

07038972

ABSTRACT:
A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

REFERENCES:
patent: 6215726 (2001-04-01), Kubo
patent: 6768698 (2004-07-01), Kono
patent: 6778464 (2004-08-01), Chung
patent: 2002043934 (2002-02-01), None
patent: 2002230972 (2002-08-01), None

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