Oscillators – Plural oscillators
Reexamination Certificate
2005-02-22
2005-02-22
Kinkead, Arnold (Department: 2817)
Oscillators
Plural oscillators
C331S185000, C331S00100A, C331S1170FE, C331S1170FE, C331S167000, C331S045000, C327S141000, C327S147000, C327S150000, C327S151000, C327S156000, C327S159000
Reexamination Certificate
active
06859109
ABSTRACT:
A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.
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Leung Gerry C. T.
Luong Howard C.
Auvinen Stuart T.
Kinkead Arnold
Pericom Semiconductor Corp.
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