Double data rate interface

Details Double data rate interface Double data rate interface

2007-03-09

2010-12-07

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S156000, C365S201000, C365S233130

Reexamination Certificate

active

07847608

ABSTRACT:
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

REFERENCES:
patent: 6111446 (2000-08-01), Keeth
patent: 6442102 (2002-08-01), Borkenhagen et al.
patent: 6950350 (2005-09-01), Kerl
patent: 2002/0180500 (2002-12-01), Okuda et al.
patent: 2003/0004667 (2003-01-01), Zumkehr
patent: 2005/0105349 (2005-05-01), Dahlberg et al.

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