Oscillators – Ring oscillators
Reexamination Certificate
1999-07-15
2001-10-16
Mis, David (Department: 2817)
Oscillators
Ring oscillators
C331S17700V, C331S175000, C327S280000, C327S287000
Reexamination Certificate
active
06304150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a delay cell. More specifically, a highly linear double-clamped delay cell with low jitter, high power-supply-rejection, and low supply voltage capabilities is disclosed.
2. Description of Related Art
Delay cells are used in phase-locked loops (PLL). A phase-locked loop generally comprises a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The VCO is an oscillator that produces a periodic wave form as an output signal, the frequency of which may be varied about some free-running frequency depending upon the value of the applied voltage. The free-running frequency is the frequency of the oscillator signal or the VCO output when the applied voltage is 0.
The phase detector receives an incoming signal and the oscillator output signal of the VCO and produces a phase detector output signal. The phase detector output signal represents the phase difference between the incoming and oscillator signals. The phase detector output signal is filtered through the low pass filter. The output of the low pass filter is the output of the PLL and the applied voltage to the VCO used to change the frequency of the VCO output. The closed-loop operation of the circuit maintains the VCO frequency locked to that of the incoming signal frequency.
If the applied signal of the VCO has the free-running frequency as an initial frequency, the PLL will acquire lock and the VCO will track the incoming signal frequency over some range, provided that the incoming signal frequency changes slowly. However, the loop will remain locked only over some finite range of frequency shift.
When the loop is operating in lock, the incoming signal and the VCO output signal fed to the phase comparator are of the same frequency, although not necessarily in phase. When the loop is trying to achieve lock, the output of the phase comparator contains frequency components at the sum and difference of the signals compared. The low-pass filter passes only the lower frequency component of the signals so that loop can obtain lock between incoming and VCO signals.
During lock, the output of the low-pass filter is the value needed to hold the VCO in lock with the incoming signal. The VCO then outputs a fixed amplitude wave signal at the frequency of the incoming signal. A fixed phase difference between the incoming and the VCO output signals to the phase comparator results in a fixed applied voltage to the VCO. Changes in the incoming signal frequency then results in change in the applied voltage to the VCO.
The limited operating range of the VCO and the feedback connection of the PLL circuit results in two frequency bands specified for a PLL: a capture range and a lock range. The capture range of the PLL is the frequency range centered about the VCO free-running frequency over which the loop can acquire lock with the input signal. The lock range of the PLL is generally wider than the capture range and is the range over which the PLL can maintain lock with the incoming signal once the PLL achieves capture. Within the capture-and-lock frequency ranges, the applied voltage drives the VCO frequency to match that of the incoming signal.
A PLL can be used in a wide variety of applications, including (1) modems, telemetry receivers and transmitters, tone decoders, AM detectors, and tracking filters; (2) demodulation of two data transmission or carrier frequencies in digital-data transmission used in frequency-shift keying (FSK) operation; (3) frequency synthesizers that provide multiples of a reference signal frequency (e.g. the carrier for the multiple channels of the citizen's band (CB) unit or marine-radio-band unit can be generated using a single-crystal-controlled frequency and its multiples generated using a PLL); and (4) FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage.
One example of a VCO implementation is a multiple-stage differential ring oscillator constructed using identical delay stages. Because each of the multiple stages are identical in construction, the delay of each stage is assumed to be the same. In such a differential ring design, the frequency of the VCO output signal is 1/(2 ×number of stages ×the delay of each stage). Thus, the frequency of the VCO output signal is 1/(8 ×the delay of each stage) for a four-stage differential ring oscillator.
The performance of such a differential ring oscillator is highly dependent on the consistency of the delay provided by each of the delay cells. In general, a delay may be provided by charging a delay capacitor to a given voltage using a stable current source. Variance in delay is introduced in currently available designs by a number of factors. One such factor is changes in the power supply voltage that cause the voltage on the delay capacitor to change. Any change in the delay in one or more of the delay cells caused by such an outside effect degrades the performance of the oscillator because instability is introduced in the frequency.
What is needed is a more robust delay cell that generates a substantially invariant delay. Ideally, the delay should be independent of variations in factors that are difficult to control such as the supply voltage temperature, and device characteristics that vary as a result of the manufacturing process. It is also desirable to provide delay cells that are highly tunable, resulting in a very linear VCO. It is further desirable to provide delay cells with low jitter and low supply voltage operation.
SUMMARY OF THE INVENTION
A delay cell is disclosed that provides a very stable delay. The delay cell is capable of operating with a low voltage power supply and has a high power supply rejection ratio, that is, the delay varies little with changes in the power supply output voltage. The design of the delay cell is such that any degradation to the performance caused by variances in the operating temperature and/or manufacturing process is minimized.
In one embodiment, the delay cell comprises a first input receiver on a first branch and a second input receiver on a second branch. The first input receiver receives a first input to control a first current on the first branch, the first branch having a first output node capacitively coupled to a power supply. The second input receiver receives a second input to control a second current on the second branch, the second branch having a second output node capacitively coupled to the power supply. The delay cell may further comprise a first current source coupled between the first output node and the power supply and a second current source coupled between the second output node and the power supply.
Preferably, the delay cell also includes a first clamp coupled between the first output node and the power supply for maintaining a first output at the first output node above a lower limit and a second clamp coupled between the second output node and the power supply for maintaining a second output at the second output node above the lower limit. The delay cell further comprise a first clamp input for supplying an input to the first clamp and a second clamp input for supplying an input to the second clamp, the clamp inputs being generated relative to the power supply.
In another preferred embodiment, the delay cell includes a tail current source coupled between ground and the first and second input receivers. Each of the first and second input receivers may be a bipolar junction transistor.
The delay cell may further include a first current diverter coupled to the first branch for diverting current on the first branch away from the first input receiver and a second current diverter coupled to the second branch for diverting current on the second branch away from the second input receiver. Each of the first and second current diverters may be a diode.
Preferably, the delay cell also includes an upper limit clamp coupled between the power supply and the first and second current diverters that
LSI Logic Corporation
Mis David
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