Double buffered graphics and video accelerator having a write bl

Details Double buffered graphics and video accelerator having a write bl Double buffered graphics and video accelerator having a write bl

1998-07-24

2000-10-03

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345521, 345503, G06F 1300

Patent

active

061280267

ABSTRACT:
A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU. At that point, the screen refresh unit signals the MIU that it has reached vertical retrace and the MIU exits write blocking mode.

REFERENCES:
patent: 5450542 (1995-09-01), Lehman et al.
patent: 5451981 (1995-09-01), Drako et al.
patent: 5657478 (1997-08-01), Recker et al.
patent: 5706034 (1998-01-01), Katsura et al.
patent: 5764964 (1998-06-01), Dwin et al.
patent: 5790138 (1998-08-01), Hsu
patent: 5796413 (1998-08-01), Shipp et al.
patent: 5966142 (1999-10-01), Harkin

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