Double buffer base gate array cell

Details Double buffer base gate array cell Double buffer base gate array cell

1993-01-29

1995-05-30

Loke, Steven Ho Yin

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257202, 257204, 257208, 257211, H01L 2710

Patent

active

054204470

ABSTRACT:
A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

REFERENCES:
patent: 4884115 (1989-11-01), Michel et al.
patent: 5187556 (1993-02-01), Nariishi et al.
Semiconductor Devices-Physics and Technology, S. M. Sze, 1985, p. 362.
Hashimoto, et al., "New Base Cell for High Density Gate Array," Custom Integrated Circuits Conference (IEEE, 1992) pp. 27.2.1-27.2.4.
Weir, et al., "A 250K-Circuit ASIC Family Using a DRAM Technology", IEEE 1990 Custom Integrated Circuits Conference, (IEEE, 1990) pp. 4.6.1-4.6.5.
Patent Abstracts of Japan, vol. 12, No. 287, (1988).
Patent Abstracts of Japan, vol. 9, No. 219, (1985).

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