Dopant profile spreading for arsenic source/drain

Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant

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257383, 257384, H01L 2967, H01L 2976, H01L 2994

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active

057898022

ABSTRACT:
An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.

REFERENCES:
patent: 5444282 (1995-08-01), Yamaguchi et al.
patent: 5523600 (1996-06-01), Kapoor
"Effects of ion implantation on formation of TiSi.sub.2 "; Park et al. Feb. 10, 1984; Journal of Vaccum Science & Technology.
I. Sakai, et al., "A NewSalicide Process (PASET) for Sub-half Micron CMOS," Proc. IEEE 1992 Symposium on VLSI Technology, Digest of Technical Papers, pp. 66-67.
Sang-Jik Kwon, et al., "As+-Preamorphization Method for Shallow p+-n Junction Formation," Japanese Journal of Applied Physics, vol. 29, No. 12, Part 02, 1 Dec. 1990, pp. L2326-L2328.
Patent Abstracts of Japan, vol. 013, No. 097 (E-723), 7 Mar. 1989 & JP 63 271972 A (Sony Corp.), 9 Nov. 1988.
H.K. Park, et al., "Effec of Ion Implantation Doping on the Formation of TiSi2," Journal of Vacuum Science & Technology A, vol. 2, No. 2, Apr.-Jun. 1984, pp. 264-268.

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