Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2006-12-29
2009-10-13
Cao, Phat X (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S017000, C257SE33008
Reexamination Certificate
active
07601980
ABSTRACT:
A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108cm−2to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.
REFERENCES:
patent: 5284782 (1994-02-01), Jeong et al.
patent: 2008/0116485 (2008-05-01), Hudait et al.
patent: 2008/0142786 (2008-06-01), Datta et al.
Brian R. Bennett et al. “Growth of InP High Electron Mobility Transistor Structures with Te Doping” Elsevier Journal of Crystal Growth 278 (2005) 695-599.
T. Ashley et al. “Novel InSb-Based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications”, Intel Corporation, Components Research, Logic Technology Development, Hillsboro, OR (4 pages).
Robert Chau et al. “Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications” Components Research, Technology & Manufacturing Group, Intel Corporation, Hillsboro, OR (4 pages).
S. Datta et al. “85nm Gate Length Enhancement and Depletion Mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications” Components Research, Technology & Manufacturing Group, Intel Corporation, Hillsboro, OR (4 pages).
Robert Chau et al. “Emerging Silicon and Non-Silicon Nanoelectronics Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications (Invited Paper)” Components Research, Logic Technology Development, Intel Corporation, Hillsboro, OR (4 pages).
M. Mori et al. “Heteroepitaxial Growth of InSb Films on a Si(001) Substrate Via AISb Buffer Layer” Applied Surface Science 216 (2003) pp. 569-574.
A. Wan et al. “Characterization of GaAs Grown by Molecular Beam Epitaxy on Vicinal Ge (100) Substrates” J. Vac. Sci. Technology B 22(4) Jul./Aug. 2004, pp. 1893-1897.
R.M. Sieg et al. “Toward Device-Quality GaAs Growth by Molecular Beam Epitaxy on Offcut Ge/SiGe/Si Substrates” J. Vac. Sci. Technology B 16(3), May/Jun. 1998, pp. 1471-1474.
S. Scholz et al. MOVPE Growth of GaAs on Ge Substrates by Inserting a Thin Low Temperature Buffer Layer, Crystal Research Technology 41, No. 2 (2006), pp. 111-116.
M. Doczy et al., US Patent Application, “Extremely High Mobility CMOS Logic”, U.S. Appl. No. 11/305,452, filed Dec. 15, 2005.
Budrevich Aaron A.
Datta Suman
Fastenau Joel M.
Hudait Mantu K.
Kavalieros Jack T.
Blakely , Sokoloff, Taylor & Zafman LLP
Cao Phat X
Intel Corporation
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