Domino style address predecoder

Details Domino style address predecoder Domino style address predecoder

1992-08-26

1994-11-29

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518904, 365191, 326106, G11C 700

Patent

active

053696212

ABSTRACT:
An address decoder having a predecoder which predecodes n pairs of true/complement address inputs into 2n memory select lines. By predecoding the address inputs in this manner, the number of pull-down FETs in the pull-down string of the NAND decoder may be minimized so as to provide area and speed advantages. Predecode is provided in a preferred embodiment by logically ANDing the respective true/complement addresses in address pairs to provide a unique predecode value to the decoder. In order to minimize the number of input lines, a decoder only receives inputs over the predecode lines having predecoded addresses unique to that decoder.

REFERENCES:
patent: 4852061 (1989-07-01), Baron et al.
patent: 4998221 (1991-03-01), Correale, Jr.
DeLano et al., "A High Speed Superscalar PA-RISC Processor", Proceedings of the Compcon Spring 1992, Digest of Papers, San Francisco, CA, Feb. 24-28, 1992.

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