Domino adder circuit having MOS transistors in the carry evaluat

Details Domino adder circuit having MOS transistors in the carry evaluat Domino adder circuit having MOS transistors in the carry evaluat

1993-11-09

1995-04-11

Mai, Tan V.

Boots, shoes, and leggings

G06F 750

Patent

active

054065062

ABSTRACT:
An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide Silicon "NMOS" transistors which are connected to and controlled by three input signals respectively. The carry evaluating logic has a carry evaluating point positioned at the top of the carry evaluating paths. The improved Domino adder circuit further has a sum evaluating logic, including a precharge transistor, an evaluation transistor, and four sum evaluating paths connected between the precharge and evaluation transistors, and connected to and controlled by the three input signals respectively. The sum evaluating logic has a sum evaluating point at the top of the sum evaluating paths. A carry generating logic is connected to and controlled by the carry evaluating point to generate a carry output signal, and a sum generating logic is connected to and controlled by the sum evaluating point to generate a sum output signal.

REFERENCES:
patent: 4733365 (1988-03-01), Nagamatsu
patent: 4851714 (1989-07-01), Hwang
patent: 4896057 (1990-01-01), Yang et al.
patent: 4899305 (1990-02-01), Needles
patent: 5128892 (1992-07-01), Ullrich
patent: 5132921 (1992-07-01), Kelley et al.

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