DMA for digital computer system

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G06F 1320

Patent

active

047730005

ABSTRACT:
An arrangement to couple at least one I/O device to the main bus between a CPU and a main memory in a digital computer system is shown to include a random access memory made up of a dedicated part of the main memory and control circuitry to allow access between addresses in the random access memory and either the CPU or the at least one I/O device, such circuitry being arranged to give priority of access to the CPU except when data is actually being transferred from the I/O device and the random access memory.

REFERENCES:
patent: Re26832 (1970-03-01), Randlev
patent: 3909799 (1975-09-01), Recks et al.
patent: 4067059 (1978-01-01), Derchak
patent: 4075691 (1978-02-01), Davis et al.
patent: 4091455 (1978-05-01), Woods et al.
patent: 4245305 (1981-01-01), Gechele et al.
Nissim, Joseph; "DMA Controller Capitalizes on Clock Cycles to Bypass CPU"; 1/78; Computer Design.

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