Patent
1992-12-11
1996-07-30
Harvey, Jack B.
395845, 395550, G06F 1328
Patent
active
055421105
ABSTRACT:
A DMA controller having an acceptance circuit, a transfer control circuit and a release ordering circuit. The acceptance circuit receives a temporary bus release request and its withdrawal from an external device, once the DMA controller acquires a bus utility right from a CPU. The transfer control circuit then interrupts bus transfer cycles under operation and holds the bus transfer parameters so as to allow a restarting of the bus transfer cycle after the withdrawal is accepted. The release ordering circuit informs the external device of the permission of temporary bus use. So, buses are temporarily released against the external device by the DMA controller of the present invention without passing through the CPU.
REFERENCES:
patent: 4688166 (1987-08-01), Schneider
patent: 4729090 (1988-03-01), Baba
patent: 4975832 (1990-12-01), Saito et al.
patent: 5072365 (1991-12-01), Burgess et al.
patent: 5195185 (1993-03-01), Marenin
patent: 5278965 (1994-01-01), Fujihira et al.
patent: 5287486 (1994-02-01), Yamasaki et al.
Auve Glenn A.
Harvey Jack B.
Kabushiki Kaisha Toshiba
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