DMA controller using a programmable timer, a transfer counter an

Details DMA controller using a programmable timer, a transfer counter an DMA controller using a programmable timer, a transfer counter an

1993-05-20

1994-02-15

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 3642405, 3642423, 36424231, G06F 1200, G06F 1300

Patent

active

052874869

ABSTRACT:
A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.

REFERENCES:
patent: 4648029 (1987-03-01), Cooper et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4751634 (1988-06-01), Burrus, Jr. et al.
patent: 4989113 (1991-01-01), Hull, Jr. et al.
patent: 5018136 (1991-05-01), Gollub
patent: 5099417 (1992-03-01), Magar et al.
"DMA Controller Matches Fast CPUs to Slow Peripherals," Electronic Design, Jul. 27, 1989.
"SCSI-Interface-Bausteine Erhohen Datentransfer-Rate", Andrew M. Davidson, National Semiconductor, Design & Elektronik, Jul. 25, 1989.

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