DMA controller using a predetermined number of transfers per req

Details DMA controller using a predetermined number of transfers per req DMA controller using a predetermined number of transfers per req

1993-11-01

1996-03-05

Swann, Tod R.

395842, 395880, 395854, 395826, G06F 1300

Patent

active

054975018

ABSTRACT:
A data transfer controller for transferring data between a memory and a peripheral unit enhances the efficiency of the DMA transfer by performing data transfer a predetermined number of times for each transfer request from the peripheral unit. The data transfer controller comprises a first register for storing address information for accessing a source area storing data to be transferred, a second register for storing first information relative to a number of data units ready to be transferred, and a third register for storing second information relative to a number of times by which a data transfer is performed in response to each transfer request from the peripheral unit. A data transfer from the source area to a destination area is performed a number of times designated by the second information in response to each transfer request. A transfer completion signal is generated when the number of data units transferred reaches the number designated by the first information.

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patent: 5056010 (1991-10-01), Huang
patent: 5062073 (1991-10-01), Masuda et al.
patent: 5104187 (1992-04-01), Debize et al.

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