DMA controller having programmable logic array for outputting co

Details DMA controller having programmable logic array for outputting co DMA controller having programmable logic array for outputting co

1989-02-07

1992-06-02

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642449, 36424231, 3642384, 364240, G06F 1206

Patent

active

051194872

ABSTRACT:
A direct memory access controller coupled to a system bus for controlling a data transfer by a direct memory access comprises an internal bus, a data handler coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles. Each data transfer between the input/output device and the memory device is controlled by the microprograms of the microsequencer in cooperation with the programmable logic array part.

REFERENCES:
patent: 4348720 (1982-09-01), Blahut et al.
patent: 4722051 (1988-01-01), Chattopadhya
patent: 4791603 (1988-12-01), Henry
patent: 4797851 (1989-01-01), Suzuki
patent: 4805137 (1989-02-01), Grant et al.
patent: 4821180 (1989-04-01), Gerety et al.
patent: 4924427 (1990-05-01), Savage et al.

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