DMA controller for memory scrubbing

Details DMA controller for memory scrubbing DMA controller for memory scrubbing

1996-02-20

1996-12-24

Beausoliel, Jr., Robert W.

Excavating

395842, 371 402, G06F 1134

Patent

active

055881122

ABSTRACT:
A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.

REFERENCES:
patent: 4488228 (1984-12-01), Grudele et al.
patent: 4604750 (1986-08-01), Manton et al.
patent: 4672613 (1987-06-01), Foxworthy et al.
patent: 4682328 (1987-07-01), Ramsay et al.
patent: 4733396 (1988-03-01), Baldwin et al.
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4888773 (1989-12-01), Arlington et al.
patent: 4905242 (1990-02-01), Popp
patent: 4907228 (1990-03-01), Bruckert et al.
patent: 5068780 (1991-11-01), Bruckert et al.
patent: 5072450 (1991-12-01), Helm et al.
patent: 5274645 (1993-12-01), Idleman et al.

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