DLL with false lock protector

Details DLL with false lock protector DLL with false lock protector

2005-01-18

2005-01-18

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06844761

ABSTRACT:
A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

REFERENCES:
patent: 5712582 (1998-01-01), Yokota et al.
patent: 5955902 (1999-09-01), Takada et al.
patent: 0005023 (1989-12-01), None
patent: 20000051784 (2000-08-01), None
Foley, David J. and Flynn, Michael P., “CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,” IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001.
Moon, Yongsan, et al, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000.

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