DLL static phase error measurement technique

Details DLL static phase error measurement technique DLL static phase error measurement technique

2003-04-03

2004-12-07

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C714S815000, C713S500000

Reexamination Certificate

active

06829548

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having: a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, communication paths (
18
), i.e., buses and wires, that transfer data among the aforementioned components of the computer system (
10
), and a clock (
20
) that is used to synchronize operations of the computer system (
10
).
In order to properly accomplish such tasks, the computer system (
10
) relies on the basis of time to coordinate its various operations. To that end, the clock (
20
) generates a system clock signal (referred to and known in the art as a “reference clock”) to various parts of the computer system (
10
). However, modern microprocessors and other integrated circuits are typically capable of operating at significantly higher frequencies, and thus, it becomes important to ensure that operations involving the microprocessor (
12
) and the other components of the computer system (
10
) use a proper and accurate reference of time.
One component used within the computer system (
10
) to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., “chip clock,” is an electronic circuit known as a delay locked loop, or “DLL.” The DLL locks an input signal to an output signal such that a delay phase between the input signal and the output signal is fixed. A typical DLL (
30
) is shown in FIG.
2
. In
FIG. 2
, the DLL (
30
) inputs a reference clock signal (shown as ref_clk) and outputs a chip clock signal (shown as chip_clk), where the reference clock and chip clock are phase aligned by the DLL (
30
). This relationship between the phases and frequencies of the reference clock and chip clock ensures that the various components within the microprocessor (
12
in
FIG. 1
) use a controlled and accounted for reference of time.
The DLL (
30
) includes the following components: a phase-frequency detector (
32
), a charge pump/filter (
34
), and a voltage-controlled delay line (
36
). The phase-frequency detector (
32
) inputs the reference clock (ref_clk) and the chip clock (chip_clk), which is fed back from the output of the DLL (
30
). The phase-frequency detector (
32
) detects a difference between a phase of the reference clock and the chip clock. If a phase of the chip clock lags behind a corresponding phase of the reference clock, the phase-frequency detector (
32
) indicates to the rest of the DLL (
30
) that the chip clock needs to be sped up. This indication is given by generating an elongated pulse to the charge pump/filter (
34
) via a fast signal (shown as fast
13
pulse).
Alternatively, if a phase of the reference clock lags behind a corresponding phase of the chip clock, the phase-frequency detector (
32
) indicates to the rest of the DLL (
30
) that the chip clock needs to be slowed down. This indication is given by generating an elongated pulse to the charge pump/filter (
34
) via a slow signal (shown as slow
13
pulse). Those skilled in the art will note that when the DLL (
30
) is “in lock,” there are still pulses on the fast and slow signals. However, in this case, i.e., when the DLL is “in lock,” the fast and slow signal pulses are equal and relatively short.
The charge pump/filter (
34
), depending on the fast and slow signals from the phase-frequency detector (
32
), either dumps or removes charge to/from a voltage signal which is used by the voltage-controlled delay line (
36
) to generate the chip clock. The chip clock is then fed back to the input of the phase-frequency detector (
32
) for continued maintenance. In effect, the DLL (
30
) generates the chip clock such that it is phase aligned with the reference clock. When this phase relationship is maintained, i.e., when the DLL is “in lock,” the timing of operations within a computer system occur as expected, and performance goals can be achieved. However, when this relationship is not maintained by the DLL (
30
), i.e., when the DLL (
30
) is “out of lock,” the operations within the computer system (
10
in
FIG. 1
) become indeterministic. Specifically, in some cases, operations may occur unexpectedly and cause computer system performance degradation.
One case in which a DLL may become “out of lock” is when there is a static phase error, i.e., an unchanging difference in phase, between the reference clock and the chip clock. In some cases, the static phase error may be caused by device variations, i.e., manufacturing variations, voltage variations, etc., in the design of the DLL. Accordingly, designers reduce static phase error by measuring and adjusting a design specification of the DLL such that an amount of static phase error introduced by device variations is minimized before the DLL is incorporated into the computer system (
10
in FIG.
1
). However, as modern microprocessors continue to operate at increasingly higher frequencies, measuring static phase error in a DLL becomes a more difficult task. In particular, the techniques and/or devices that are used to measure static phase error may contribute a large amount of error to the static phase error measurement, making the static phase error measurement inaccurate.
SUMMARY OF INVENTION
In one aspect, an apparatus for measuring static phase error in a delay locked loop comprises a first test stage arranged to receive a reference clock, a chip clock, and a control signal; and a second test stage arranged to receive the reference clock, the chip clock, and a complement of the control signal, wherein, dependent on the control signal, the first test stage outputs a first test signal, and wherein dependent on the complement of the control signal, the second test stage outputs a second test signal, wherein static phase error in the delay locked loop is determined dependent on the first test signal and the second test signal.
In another aspect, a system for measuring static phase error in a delay locked loop comprises delay locked means for generating a chip clock dependent on a reference clock; means for generating a first test signal and a second test signal dependent on the reference clock, the chip clock, and a control signal; means for comparing a phase of the first test signal to a phase of the second test signal; and means for determining a static phase error between the phase of the first test signal and the phase of the second test signal.
In another aspect, a method for measuring static phase error in a delay locked loop comprises generating a chip clock dependent on a reference clock; obtaining a first static phase error measurement between the chip clock and the reference clock dependent on a first value of a control signal; obtaining a second static phase error measurement between the chip clock and the reference clock dependent on a second value of the control signal; and measuring the static phase error in the delay locked loop by comparing a value of the first static phase error measurement and a value of the second static phase error measurement.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5815016 (1998-09-01), Erickson
patent: 6194916 (2001-02-01), Nishimura et al.
patent: 6448756 (2002-09-01), Loughmiller
patent: 6470060 (2002-10-01), Harrison
patent: 6556489 (2003-04-01), Gomm et al.
patent: 6700414 (2004-03-01), Tsujino

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