DLL-(delay-locked-loop) circuit

Details DLL-(delay-locked-loop) circuit DLL-(delay-locked-loop) circuit

2003-01-13

2004-06-08

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06747496

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a DLL (Delay-Locked Loop) circuit.
BACKGROUND OF THE INVENTION
In a DLL circuit, assuming a large frequency range of the input clock, the problem arises that the delay time of the delay line in the locked state of the circuit can amount to a clock period of the input clock or else an integer multiple thereof. With the aid of a DLL circuit, it is possible to subdivide a clock period of the input clock into a plurality of phases. Various square-wave signals can then be derived from these phases with the aid of an additional logic.
A previously known solution is described in more detail in the Canadian document CA 2309522-A1, published on Jun. 22, 2001. An apparatus and a method are presented, which are distinguished by counting of the rising edges within the delay line, during a clock period of the input clock. A further known solution is based on the use of a replica delay line and was published with the title “An all-analog multiface delay-locked loop using a replica Delayline for wide-range operation and low-jitter performances” in IEEE Journal of Solid-State-Circuits, Vol. 35, No. 3, March 2000.
FIG. 1
illustrates a block diagram of a customary DLL (Delay-Locked Loop) circuit. In the locked state, a delayed input clock signal
7
(clkd) is delayed exactly one period duration with respect to the input clock signal
6
(clk). If the delay of the delay device
1
changes, a phase shift arises between the input clock signal
6
(clk) and the delayed input clock signal
7
(clkd). This phase shift is identified by the phase detector
2
, whereupon the latter causes an electrical energy source
3
, for example a charge pump
3
, to send current pulses into a filter device
4
. On account of this, a feedback signal
5
changes and the regulating voltage for changing the delay time (delay) at the input of the delay device
1
alters the delay time of the delay line
1
, so that the phase shift between the input clock signal
6
(clk) and the delayed input clock signal
7
(clkd) decreases again.
However, if the input frequency can vary in a large range, which is equivalent to a large change range of the delay time (delay), it is possible, in the locked state, for the delayed input clock
7
clkd to be delayed by an integer multiple of the period duration of the input clock
6
with respect to the input clock signal
6
. This represents an unacceptable state and should be prevented.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a DLL circuit which, despite a large input frequency range of the input clock, ensures that the delay time of the delay line in the locked state amounts to precisely one clock period. It is likewise an object of the present invention to provide a method for operating a DLL circuit in order to ensure that the delay time of the delay line in the locked state amounts to only one clock period of the input clock.
According to the invention, this object is achieved by means of the DLL circuit specified in claim 1 and by means of the method according to claim 20.
The idea on which the present invention is based consists in generating a signal Q, whose frequency is approximately proportional to the reciprocal of the delay time (delay), and deriving a further signal from the signal Q, from which the fact of whether the delay of the delay device lies in the region of a period duration of the input clock can be identified.
In the present invention, the problem mentioned in the introduction is solved in particular by virtue of the fact that a superordinate regulating circuit is placed above a standard DLL regulating circuit and identifies whether the delay between the input clock signal (clk) and a delayed input clock signal (clkd) lies in the region of a period duration. If that is not the case, then the superordinate regulating circuit intervenes in order to minimize the regulation deviation. If the delay between the input clock (clk) and the delayed input clock (clkd) is in the region of a period duration of the input clock, then the subordinate standard DLL regulating circuit corrects the regulation deviation.
Advantageous developments and improvements of the respective subject matter of the invention can be found in the subclaims.
In accordance with one preferred development, the device for generating the signal Q has a flip-flop chain comprising more than two flip-flops, which exhibit feedback via an inverter.
In accordance with a further preferred development, the device for generating the signal Q has exactly one delay element of the delay device in circuitry terms between two flip-flops of the flip-flop chain.
In accordance with a further preferred development, a signal evaluation device has a device for comparing frequencies.
In accordance with a further preferred development, the signal evaluation device has a device for identifying a state change, in particular in the device for generating the signal Q.
In accordance with a further preferred development, a DLL circuit has both a state detection device and a frequency comparison device.


REFERENCES:
patent: 5970110 (1999-10-01), Li
patent: 6259288 (2001-07-01), Nishimura
patent: 6614287 (2003-09-01), Gauthier et al.
patent: 2002/0000855 (2002-01-01), Lee

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