DLL circuit having duty cycle correction and method of...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S149000, C327S156000

Reexamination Certificate

active

07821310

ABSTRACT:
A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.

REFERENCES:
patent: 6765976 (2004-07-01), Oh
patent: 6967514 (2005-11-01), Kizer et al.
patent: 7184509 (2007-02-01), Cho et al.
patent: 7521974 (2009-04-01), Kirschenmann
patent: 7598783 (2009-10-01), Shin et al.
patent: 7633324 (2009-12-01), Yun et al.
patent: 2007/0279109 (2007-12-01), Kirschenmann
patent: 2008/0100356 (2008-05-01), Lee
patent: 2008/0191767 (2008-08-01), Koo
patent: 2008/0278206 (2008-11-01), Kim et al.
patent: 2009/0295446 (2009-12-01), Yun et al.
patent: 1020070016737 (2007-02-01), None
patent: 1020080069756 (2008-07-01), None

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