DLL circuit capable of preventing locking in an antiphase state

Details DLL circuit capable of preventing locking in an antiphase state DLL circuit capable of preventing locking in an antiphase state

2003-04-29

2004-11-02

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C375S376000

Reexamination Certificate

active

06812759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DLL (Delay-Locked Loop) circuit, which is a phase-locked circuit.
2. Description of the Related Art
As a result of the advances in the acceleration of processing speeds in systems that use semiconductor integrated circuit devices in recent years, memory devices have come into use such as DRAM (Dynamic Random Access Memory) and SDRAM (Synchronous DRAM) that operate at clocks of several hundred MHz. In addition, the power supply voltage has also been decreased to meet the demand for lower power consumption, and semiconductor integrated circuit devices that operate at voltages as low as 1.5 V have come into use.
In order to prevent increase in noise and malfunctioning of the system in systems such as these that operate at high speed and moreover at low voltage, it is important to suppress fluctuation in the characteristics of the output buffer circuit that is provided in the semiconductor integrated circuit device to cope with fluctuations in the power supply voltage and ambient temperature and variation in element characteristics.
In systems that include semiconductor integrated circuit devices such as DDR(Double Data Rate)-SDRAM that operate at high speed, DLL circuits, which are phase-locked circuits, are typically used to match the timing of data output of output buffer circuits that are provided in the semiconductor integrated circuit devices to the system clock. A DLL circuit is a circuit that uses an output dummy circuit having a propagation delay that is similar to the output buffer circuit to monitor the amount of delay of the output buffer circuit from the system clock, generates an internal clock for compensating the amount of delay from the system clock, and supplies the generated internal clock to the output buffer circuit, thereby synchronizing the timing of the data output of the output buffer circuit to the system clock.
We now refer to
FIG. 1
, which is a block diagram showing the construction of a DLL circuit of the prior art. As shown in
FIG. 1
, the DLL circuit of the prior art is a construction that includes:
output dummy circuit
1
having a propagation delay that is similar to that of an output buffer circuit that is provided in a semiconductor integrated circuit device;
delay element
2
for delaying a system clock (reference clock Ref) that prescribes the operation timing of the semiconductor integrated circuit device, supplying the delayed clock to output dummy circuit
1
, and supplying this delayed clock as internal clock CLK; and
phase determination circuit
3
for comparing the phases of reference clock Ref and feedback signal Fb that is supplied as output from output dummy circuit
1
and supplying control signal Q for altering the amount of delay of delay element
2
based on the comparison result.
Phase determination circuit
3
compares the phases of reference clock Ref and feedback signal Fb that is supplied from output dummy circuit
1
, supplies control signal Q for increasing the amount of delay of delay element
2
when the phase of feedback signal Fb is advanced from reference clock Ref, and supplies control signal Q for decreasing the amount of delay of delay element
2
when the phase of feedback signal Fb is retarded from reference clock Ref. By means of this operation, the DLL circuit operates such that the phase of feedback signal Fb that is supplied from output dummy circuit
1
matches the phases of reference clock Ref. Properly speaking, the operation of DLL circuit is controlled such that the phase of feedback signal Fb coincides with a time that is delayed one cycle from the phase of reference clock Ref.
When the phases of feedback signal Fb and reference clock Ref match, internal clock CLK is a signal having a phase that is advanced from that of feedback signal Fb by exactly the propagation delay of output dummy circuit
1
, and that is also advanced from the phase of reference clock Ref by exactly the propagation delay of output dummy circuit
1
. Using internal clock CLK to operate the output buffer circuit therefore causes data signals to be supplied as output from the output buffer circuit with the same phase as reference clock Ref.
We next refer to
FIG. 2
, which is a circuit diagram showing an example of the construction of the phase determination circuit shown in
FIG. 1
, and
FIGS. 3A and 3B
, which are timing charts showing the operation of the phase determination circuit shown in FIG.
1
.
As shown in
FIG. 2
, phase determination circuit
3
is a construction that includes: two first flip-flops
31
1
and
31
2
to which reference clock Ref is applied as input; and second flip-flop
32
to which the output of first flip-flops
311
and
312
is applied as input and that generates control signal Q (phase determination result) and the inverted signal Qb of this control signal Q for controlling the amount of delay of the above-described delay element
2
. First flip-flops
31
1
and
31
2
and second flip-flop
32
are each made up from two NAND gates, the output of each NAND gate of a pair being fed back as input to the other NAND gate. Power supply voltage VDD and feedback signal Fb are applied as input to one of the NAND gates of first flip-flop
312
. The input capacitance of each NAND gate to which reference clock Ref and feedback signal Fb are applied is set to substantially the same value.
In a construction of this type, when reference clock Ref and feedback signal Fb are both “LOW” and feedback signal Fb becomes “HIGH” before reference clock Ref, as shown in
FIG. 3A
, a “LOW” signal is supplied as control signal Q. On the other hand, when reference clock Ref and feedback signal Fb are both “LOW” and reference clock Ref becomes “HIGH” before feedback signal Fb as shown in
FIG. 3B
, a “HIGH” signal is supplied as control signal Q. The delay amount of delay element
2
is controlled based on these phase determination results.
FIGS. 3A and 3B
show a case in which the phases of reference clock Ref and feedback signal Fb are compared with the rising edge of feedback signal Fb as the standard, but the phases may be compared with the rising edge of reference clock Ref as standard, or the phase comparison may be realized with the falling edge of either reference clock Ref or feedback signal Fb as the standard.
We next refer to
FIG. 4
, which is a circuit diagram showing an example of the construction of the delay element that is shown in FIG.
1
. In addition,
FIG. 5
is a circuit diagram showing an example of the construction of the delay chain circuit that is shown in
FIG. 4
, and
FIG. 6
is a circuit diagram showing an example of the construction of the CLK mix circuit that is shown in FIG.
4
.
FIG. 4
is a construction typically referred to as a digital delay element.
As shown in
FIG. 4
, delay element
2
is a construction that includes: delay chain circuit
21
for supplying signals in which reference clock Ref has been delayed in steps at relatively large time intervals; and delay amount interpolation circuit
22
for interpolating the delay amount of each step that is supplied from delay chain circuit
21
.
As shown in
FIG. 5
, delay chain circuit
21
is a construction that is provided with: a plurality of inverter circuits connected in a series, and output ports (
1
,
2
,
3
, . . . , N, N+1, N+2, . . . , Nmax; where N is a positive integer), one output port being provided for each two inverter circuits. In a construction of this type, reference clock Ref is delayed by each of the inverter circuits, and, reference clock Ref is supplied as output from each output port, the amount of delay of this reference clock Ref depending on the number of inverter circuits that are inserted between that output port and the input port of reference clock Ref. In this case, the amount of delay realized by two inverter circuits (the difference in delay amount between adjacent output ports) is on the order of 400 ps. Delay element
2
that is shown in
FIG. 4
is a construction that selects the output signals (M and

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