DLL circuit and semiconductor device having the same

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S149000

Reexamination Certificate

active

07876138

ABSTRACT:
A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.

REFERENCES:
patent: 7046060 (2006-05-01), Minzoni et al.
patent: 7336752 (2008-02-01), Vlasenko et al.
patent: 7592846 (2009-09-01), Mehas et al.
patent: 7724051 (2010-05-01), Tomar et al.
patent: 2004/0125905 (2004-07-01), Vlasenko et al.
patent: 2009/0189658 (2009-07-01), Tomar et al.
patent: 2010/0102862 (2010-04-01), Takahashi et al.
patent: 2010/0201413 (2010-08-01), Miyano
patent: 2010/0213991 (2010-08-01), Fukuda

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