DLL circuit and method of generating timing signals

Details DLL circuit and method of generating timing signals DLL circuit and method of generating timing signals

2001-04-04

2004-12-28

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S392000, C327S141000, C327S161000

Reexamination Certificate

active

06836165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DLL (delay locked loop) circuit, a semiconductor device using the same, and a method of generating timing signals.
2. Description of the Related Art
The operation of a semiconductor device such as a memory circuit, an interface circuit and a CPU are controlled based on a reference clock signal supplied from an external apparatus. In recent years, the memory circuit is required to operate correctly at a speed as high as about 400 MHz with increase of the operation speed of the semiconductor device. For example, a synchronous type DRAM carries out a data output in synchronism with the reference clock signal. Such a synchronous type DRAM needs to correctly operate in synchronism with a rising edge and a falling edge of the reference clock signal with about 2.5-ns period. In the other words, this is means that the synchronous type DRAM is necessary to operate at the timing of half period of 1.25 ns.
In the synchronous type DRAM, the operation is controlled based on internal clock signals which are generated based on the reference clock signal. However, in order to guarantee a correct high-speed operation, it is necessary that the phase of an external clock signal as a reference clock signal is coincident with that of the internal clock signal, or that the phase difference between the external clock signal and the internal clock signal is defined strictly. For the purpose of the coincidence in the phase, a DLL circuit is used.
That is, in the DLL circuit, a variable delay circuit delays the external clock signal such that the delayed signal is outputted as the internal clock signal. The phase of the internal clock signal generated thus is compared with the phase of the external clock signal by a phase comparing circuit, and a feedback phase control is carried out based on a phase deference to change the delay quantity of the variable delay circuit. In this way, the phase of the internal clock signal is coincident with the phase of the external clock signal.
Next, referring to
FIG. 1
, the structure of a conventional synchronous type DRAM as a first conventional example will be described. The first conventional example of the synchronous type DRAM is composed of a DLL circuit
201
, a logic circuit
203
, and a memory section
202
. The logic circuit
203
is composed of a logic circuit
203
-
1
and flip-flop circuits
203
-
2
and
203
-
3
. The memory section
202
is composed of a column control circuit
202
-
5
, a memory array
202
-
1
, a Y decoder (YDEC)
202
-
2
, an I/O circuit
202
-
3
, a latch circuit
202
-
4
, a row control circuit
202
-
7
, and an X decoder (XDEC)
202
-
6
. Because the connection structure of the memory section
202
and the operation thereof are well known, the detailed description is omitted.
An internal clock signal S
1
is outputted from the DLL circuit
201
based on an external clock signal. The internal clock signal S
1
is supplied to an inversion clock terminal of the flip-flop circuit
203
-
2
and a clock terminal of the flip-flop circuit
203
-
3
. The logic circuit
203
-
1
generates control signals C
1
and C
2
based on the external control signal. The control signal C
1
is supplied to the flip-flop circuit
203
-
2
, and the control signal C
2
is supplied to the flip-flop circuit
203
-
3
. The flip-flop circuit
203
-
3
outputs a read enable signal RE′ to the column control circuit
202
-
5
of the memory section
202
. Also, the flip-flop circuit
203
-
2
outputs a latch signal to the latch circuit
202
-
4
of the memory section
202
.
Next, referring to
FIGS. 2A
to
2
G, the operation of the synchronous type DRAM shown in
FIG. 1
will be described. When a read command is supplied to the logic circuit
203
-
1
of
FIG. 2B
as an external control signal, the flip-flop circuit
203
-
3
generates the read enable signal of
FIG. 2D
based on the control signal C
2
shown in
FIG. 2C
in synchronism with the internal clock signal S
1
. In this way, data A is read out from the memory section
202
as shown in FIG.
2
E. The flip-flop circuit
203
-
2
generates the latch signal of
FIG. 2G
based on the control signal C
1
of
FIG. 2F
in synchronism with the falling edge of the internal clock signal S
1
of FIG.
2
A. The data A is latched by the latch circuit
202
-
4
at the timing of the falling edge of the latch signal.
The synchronous type DRAM is composed of a section such as the I/O circuit
202
-
3
and the latch circuit
202
-
4
to carry out an operation in synchronism with the external clock signal, and a section to carry out an operation such as a read operation of data from the memory array in asynchronism with the external clock signal. This is constraint in case of the operation control of the synchronous type DRAM. That is, the timing of the synchronous operation is specified based on the standard of a product. Also, the timing of the asynchronous operation is determined based on the characteristics of transistors in the memory section and the delay due to inner wiring lines. Therefore, the latch circuit
202
-
4
cannot change the timing of the data output in accordance with the operation speed of the data read. Oppositely, the timing of the data read cannot be controlled from an external apparatus. Therefore, the rising timing of the read enable signal RE′ shown in
FIG. 2D
needs to be adjusted to an optimal timing such that the latch signal is generated when data is read out from the memory array
202
-
1
. In other words, the time period from the rising edge of the read enable signal RE′ to the falling edge of the latch signal needs to be adjusted to the necessary and minimum time period for the correct data read operation.
For example, in the synchronous type DRAM, it is necessary to carry out a precharging operation of read lines immediately before the read operation. For this purpose, it is necessary to generate the second internal clock signal earlier than the internal clock signal synchronous with the external clock signal by a little time, e.g., by about 0.5 ns.
However, in the structure of
FIG. 1
, the read enable signal RE′ synchronous with the internal clock signal S
1
is used for the data read operation. Therefore, it is only possible to adjust the timing in units of periods or half periods of the external clock. As mentioned above, it is not possible to carry out strict timing adjustment in the time width shorter than the half period.
Also,
FIG. 3
shows a second conventional example which uses a fixed delay circuit. Referring to
FIG. 3
, the second conventional example is composed of a DLL circuit
101
, a latch circuit
102
and a fixed delay circuit
105
. The DLL circuit
101
carries out delay control to an external clock signal Rclk and generates an internal clock signal
1011
. The signal
1011
is supplied to the latch circuit
102
. An activating signal
103
is supplied to the latch circuit
102
. The latch circuit
102
outputs a signal
104
in response to the activating signal
103
. The fixed delay circuit
105
delays the signal
104
and outputs a read enable signal RE′
106
. The fixed delay circuit
105
is composed of a large number of delay elements and a total delay quantity of the delay elements is predetermined and fixed to the time t
1
. The signal RE′
106
delayed thus is used in an operation section of the synchronous type DRAM, e.g., the memory section. It is desired that the read enable signal RE′
106
leads a signal of
FIG. 4C
generated in response to the rising edge of the internal clock signal S
1
by a time t
1
.
The operation of the second conventional example shown in
FIG. 3
will be described. It is supposed that the internal clock signal S
1
1011
shown in
FIG. 4A
is outputted from the DLL circuit
101
. In this example, the external clock signal Rclk has a high frequency. Therefore, the internal clock signal S
1
1011
also has a high frequency. When the signal
104
is outputted from the latch circuit
102
in respo

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