DLL circuit and DLL control method

Details DLL circuit and DLL control method DLL circuit and DLL control method

2001-07-12

2004-02-10

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S161000, C331SDIG002

Reexamination Certificate

active

06690214

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a delay locked loop (DLL) circuit and a DLL control method and more particularly to DLL circuit and DLL control method for locking and outputting rising and falling phases of a clock signal.
BACKGROUND OF THE INVENTION
In a semiconductor device, such as a semiconductor memory, an external clock signal is typically used to synchronize data transfer. In such a semiconductor memory, data can be input and output on rising and falling edges of the external clock signal. A delay locked loop (DLL) circuit can be incorporated in such a device in order to generate an internal clock signal that is synchronized with the external clock signal. A DLL circuit uses a variable delay to delay an internal clock signal so that the edges become synchronized (phase matching) with the external clock signal. Thus, an accurate DLL circuit requires a circuit for accurately generating a phase delay.
Referring now to
FIG. 1
, a block schematic diagram of a conventional DLL circuit is set forth and given the general reference character
100
.
Conventional DLL circuit
100
synchronizes an output clock signal with both the rising and falling edges of an external clock signal.
Conventional DLL circuit
100
includes a first DLL system
101
and a second DLL system
102
. First DLL system
101
receives an external clock signal D
101
and a reference clock D
102
and generates a first internal clock signal D
104
. Second DLL system
102
receives external clock signal D
101
and reference clock D
102
and generates a second internal clock signal D
106
.
First DLL system
101
includes a first phase detection circuit
111
, a first arbitrary phase generation circuit
112
, and a buffer
113
. First phase detection circuit
111
receives the external clock signal D
101
and first internal clock signal D
104
as inputs and generates a phase detection result signal D
103
. First arbitrary phase generator circuit
112
receives reference clock D
102
and phase decision result signal D
103
. First arbitrary phase generator circuit
112
delays the phase of reference clock signal D
102
based upon the value of phase decision result signal D
103
to generate delayed clock signal D
102
′. Buffer
113
receives delayed clock signal D
102
′ and generates first internal clock signal D
104
.
First internal clock signal D
104
is input into first phase decision circuit
111
. First phase decision circuit compares the rising edge of external clock signal D
101
with first internal clock signal D
104
and outputs first phase decision result signal D
103
. First phase decision result signal D
103
indicates the phase difference between the rising edges of external clock signal D
101
and first internal clock signal D
104
. When external clock signal D
101
and first internal clock signal D
104
having rising edges that are coincident with each other in their phases, delayed clock signal
102
′ becomes locked in its phase.
Second DLL system
102
includes a second phase detection circuit
114
, a second arbitrary phase generation circuit
115
, and a buffer
116
. Second phase detection circuit
114
receives the external clock signal D
101
and second internal clock signal D
106
as inputs and generates a phase detection result signal D
105
. Second arbitrary phase generator circuit
115
receives reference clock D
102
and phase decision result signal D
105
. Second arbitrary phase generator circuit
115
delays the phase of reference clock signal D
102
based upon the value of phase decision result signal D
105
to generate delayed clock signal D
102
″. Buffer
116
receives delayed clock signal D
102
″ and generates second internal clock signal D
106
.
Second internal clock signal D
106
is input into second phase decision circuit
114
. Second phase decision circuit compares the falling edge of external clock signal D
101
with second internal clock signal D
106
and outputs second phase decision result signal D
105
. Second phase decision result signal D
105
indicates the phase difference between the falling edges of external clock signal D
101
and second internal clock signal D
106
. When external clock signal D
101
and second internal clock signal D
106
having falling edges that are coincident with each other in their phases, delayed clock signal
102
″ becomes locked in its phase.
Referring now to FIGS.
2
(
a
)-(
c
), a timing diagram illustrating external clock signal D
101
, first internal clock signal D
104
, and second internal clock signal D
106
is set forth.
The timing diagram of FIGS.
2
(
a
)-(
c
) illustrates signals generated by conventional DLL circuit
100
when the high edged pulse width of first and second internal clock signals (D
104
and D
106
) is greater than the high pulse width of external clock signal D
101
. It is noted that only one edge of first internal clock signal D
104
(rising edge) and second internal clock signal D
106
(falling edge) has a phase that is locked with external clock signal D
101
. Thus, the pulse widths of the first and second internal clock signals (D
104
and D
106
) is not set by the phase of external clock signal D
101
. So, even though the first and second internal clock signals (D
104
and D
106
) have the same period (T
1
) as the external clock signal D
101
, the waveforms do not match.
Referring now to FIGS.
3
(
a
)-(
c
), a timing diagram illustrating external clock signal D
101
, first internal clock signal D
104
, and second internal clock signal D
106
is set forth.
The timing diagram of FIGS.
3
(
a
)-(
c
) illustrates signals generated by conventional DLL circuit
100
when the high edged pulse width of first and second internal clock signals (D
104
and D
106
) is less than the high pulse width of external clock signal D
101
. It is noted that only one edge of first internal clock signal D
104
(rising edge) and second internal clock signal D
106
(falling edge) has a phase that is locked with external clock signal D
101
. Thus, the pulse widths of the first and second internal clock signals (D
104
and D
106
) is not set by the phase of external clock signal D
101
. So, even though the first and second internal clock signals (D
104
and D
106
) have the same period (T
1
) as the external clock signal D
101
, the waveforms do not match.
In conventional DLL circuit
100
first DLL system
101
and second DLL system
102
each have an arbitrary phase generator circuit (
112
and
115
) in order to create internal clock signals (D
104
and D
106
) that are locked, respectively, with a rising edge and falling edge of external clock signal D
101
. Arbitrary phase generator circuits (
112
and
115
) require a large amount of chip area compared to the other circuits in the conventional DLL circuit
100
. In order to generate a clock with reduced jitter having an arbitrary phase using arbitrary phase generator circuit (
112
and
115
), a large amount of chip area may be required, which increases manufacturing costs. Also, power consumption of arbitrary phase generator circuits (
112
and
115
) is a large portion of the power consumed in the conventional DLL circuit
100
.
Also, because a separate internal clock signal (D
104
and D
106
) are generated in order to have internal clocks that are locked in phase with the rising and falling edges, respectively, of external clock signal D
101
, a circuit that is clocked off one edge may receive a different signal than one clocked off the opposite edge. This can increase signal routing and consume chip area.
In view of the above discussion, it would be desirable to provide a DLL circuit that may be capable of outputting a single system clock signal in synchronism with both rising and falling edges of an external clock signal. It would also be desirable to provide a DLL control method for controlling the DLL circuit. It would be desirable to provide a DLL circuit having reduced power consumption compared to conventional approaches. It would also be desirable to provide a DLL circuit, which occupies a reduced chip a

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