DLL circuit and control method therefor

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S149000

Reexamination Certificate

active

08063679

ABSTRACT:
Jitter is stably reduced. An input clock signal (CLKi) is outputted as an output clock signal (CLKo) via a voltage controlled delay circuit (12), and in addition a delay amount in the voltage controlled delay circuit (12) is controlled based on a result of a phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo). A phase comparison result judging circuit (15) adds up results of phase comparison of the input clock signal (CLKi) and the output clock signal (CLKo) over a prescribed time, and controls the delay amount based on a distribution of addition results.

REFERENCES:
patent: 6987409 (2006-01-01), Kim et al.
patent: 7111185 (2006-09-01), Gomm et al.
patent: 7239188 (2007-07-01), Xu et al.
patent: 7486119 (2009-02-01), Lee
patent: 2001/0028266 (2001-10-01), Taniguchi
patent: 2003/0067332 (2003-04-01), Mikhalev et al.
patent: 2003/0128622 (2003-07-01), Graaff
patent: 2004/0177286 (2004-09-01), Gauthier et al.
patent: 2001-290555 (2001-10-01), None

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