Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-02-01
2002-11-05
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000, C331S00100A
Reexamination Certificate
active
06476653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delayed lock loop (DLL), which is a circuit whereby the timing of a clock is stabilized, and, in particular, relates to a DLL circuit wherein the timing of the control clock can be adjusted according to an external load connected to an output terminal in a short time.
2. Description of the Related Art
High-speed memory devices constituted by SDRAMs that operate in synchronism with an external clock are widely used. Such clock-synchronized memory devices incorporate therein a timing control circuit consisting of a delayed lock loop (DLL) circuit in order to input and output data synchronously with an external clock. Such a DLL circuit is disclosed for example in Laid-open Japanese Patent Publication No. H10-112182 applied for by the present applicant.
The DLL circuit referred to above generates a control clock whose phase is coincident with or in a prescribed phase relationship with the supplied external clock, and this control clock controls the operating timing of the input buffer and/or output buffer. In general terms, the DLL circuit comprises a variable delay circuit that delays a reference clock, a dummy delay circuit that further delays the clock of the output of this variable delay circuit by the amount of the delay time of the input buffer and/or output buffer, and a phase comparator and delay control circuit that compare the phases of the reference clock and the delayed clock of the output of the dummy delay circuit and thereby control the amount of delay of the variable delay circuit such that the phases of the two clocks agree. In the locked condition in which the phases of the reference clock and delayed clock coincide, the data output that is output from the data output buffer in response to the control clock of the output of the variable delay circuit coincides with the phase of the external clock.
Memory devices or other devices incorporating a DLL circuit as described above are usually mounted on a printed circuit board or a module circuit board. The output terminal of the data output buffer whose operating timing is controlled by the control clock generated by the DLL circuit is connected to wiring such as of the printed circuit board where it is mounted. Consequently, the time required for operation of the data output buffer is different depending on the magnitude of this external load.
However, the external load that is connected to the output terminal of such a data output buffer depends on the construction of the wiring of the printed circuit board or module circuit board where it is mounted and cannot be predicted at the stage of design of the device itself. It may therefore be considered that if the delay time of the dummy output buffer provided in the feedback loop of the DLL circuit is made fixed, the delay time required for operation of the data output buffer in the condition in which the device is installed in the system will not match the fixed set operating time of the dummy output buffer. As a result, the timing of the control clock produced by the DLL circuit becomes non-optimal.
When the device is installed in the system, for example in the initialization condition after actuation of the power source, it is therefore desired to set the amount of delay of the delay circuit in the feedback loop taking into account external load.
On the other hand, since the device outputs are connected to a bus that is common to a plurality of devices, it is not possible to adjust each of a plurality of devices simultaneously in the initialization condition; rather, adjustment must be carried out for each of the devices, one by one. In this situation, it is demanded to be able to adjust the delay amounts in the feedback loop for each individual device. However, with the DLL circuit proposed in the above Laid-open Japanese Patent Publication No. H10-112182, in order to adjust the timing, it is necessary to perform a phase comparison operation of the reference clock and the delayed clock a plurality of times, as well as adjustment of the amount of delay. If adjustment in accordance to the external load is performed for each device, a long time is required for timing adjustment of the system as a whole.
An object of the present invention is therefore to provide a DLL circuit capable of generating a control clock which is synchronized with a reference clock and which has optimum timing adapted to an external load connected to the output terminal of the device.
A further object of the present invention is to provide a DLL circuit capable of generating a control clock which is synchronized with a reference clock and which has optimum timing adapted to an external load connected to the output terminal of the device, in which adjustment to the optimum timing can be achieved in a short time.
SUMMARY OF THE INVENTION
In order to achieve the above object, in a first aspect of the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, the operating delay time of an output buffer is measured and the timing of the control clock is adjusted in accordance with this operating delay time. The DLL circuit comprises: a first variable delay circuit that receives the reference clock and outputs a clock delayed by a controlled delay time; a second variable delay circuit that receives the output clock of the first variable delay circuit and outputs a delayed clock delayed by a prescribed delay time; and a phase comparison/delay control circuit that compares the phase of the reference clock and the delayed clock and controls the amount of delay of the first variable delay circuit such that the phase of the reference clock and of the delayed clock are in coincidence. Also, the operating delay time of said output buffer, which is different depending on an external load, is measured, and the delay amount of the second variable delay circuit in the feedback loop of the DLL circuit is adjusted in accordance with the measured operating delay time of the output buffer. As a result, the timing of the output clock of the first variable delay circuit delay circuit is adjusted in accordance with the magnitude of the external load. This output clock or the output clock of a separate variable delay circuit subject to the same delay control is then utilized as a control clock.
In order to achieve the above object, in another aspect of the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, wherein an output buffer supplies an output signal to an output terminal in response to the control clock, the DLL circuit comprises: a first variable delay circuit that receives the reference clock and outputs a clock delayed by a controlled delay time; a second variable delay circuit that receives the output clock of the first variable delay circuit and outputs a delayed clock delayed by a prescribed delay time; a phase comparison/delay control circuit that compares the phase of the reference clock and the delayed clock and controls the amount of delay of the first variable delay circuit such that the phase of the reference clock and of the delayed clock are in a prescribed relationship; and a delay measurement circuit that measures an operating delay time of the output buffer and sets the delay amount of the second variable delay circuit in accordance with the measured operating delay time.
With the above construction, the timing of the control clock can be finely adjusted in accordance with the output load of the output terminal, so that a control clock of optimum timing can be generated.
Furthermore, in a preferred embodiment of the present invention, in the above invention, the delay measurement circuit measures the time from the timing of the control clock to the timing of the output signal of the output buffer. Since the operating delay time of the output buffer is mea
Arent Fox Kintner Plotkin & Kahn
Callahan Timothy P.
Luu An T.
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