DLL circuit

Details DLL circuit DLL circuit

2005-11-29

2005-11-29

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06970028

ABSTRACT:
DLL circuit with a small minimum delay time while allowing a wide range of adjustment of the delay time. The DLL circuit according includes a first delay circuit for delaying an input clock signal (CLK1) to output a plurality of delayed clock signals (T1to TN), a first selector (7) for selecting a first delayed clock signal (CLK_E) and a second delayed clock signal (CLK_O) from among the plurality of delayed clock signals (T1to TN), for output, a second delay circuit (3) for delaying the input clock signal (CLK1) to generate a slightly delayed clock signal (CLKD), a second selector (4) for selecting two selected clock signals (FDLE, FDLO) from among the slightly delayed clock signal (CLKD), first delayed clock signal (CLK_E), and second delayed clock signal (CLK_O), and a delay synthesis circuit (5) for generating an internal clock signal (CLKIN) from the selected clock signals (FDLE, FDLO), for output.

REFERENCES:
patent: 6100735 (2000-08-01), Lu
patent: 6535043 (2003-03-01), Chen
Tatsuya Matano, et al., “A 1-Gb/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer”, 2002 VLSI Symposium: Thesis No. 9-1.

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