DLL circuit

Details DLL circuit DLL circuit

1999-05-26

2001-02-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S158000

Reexamination Certificate

active

06194930

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a delay locked loop (hereinafter referred to simply as DLL) circuit, which delays a supplied clock, and automatically synthesizes a clock having a phase of a predetermined relation with the phase of this clock, and more particularly to a DLL circuit, which is capable of shortening the time it takes to achieve a locked state at normal operation start.
DESCRIPTION OF THE RELATED ART
FIG. 1
is a diagram showing an example of a conventional DLL circuit. The DLL circuit of
FIG. 1
synthesizes a control clock c-clk
1
for outputting data output Dout at a timing in synchronization with the phase of an external clock CLK which is supplied from the outside. In the DLL circuit, a delay-locked loop circuit for a first clock c-clk and a delayed clock d-i-clk which delays this first clock c-clk by a predetermined quantity is formed, and this loop circuit adjusts the timing of these clocks, and in accordance with a delay control signal &phgr;
E
generated thereby, adjusts a delay quantity of a variable delay circuit
11
.
In the DLL circuit of
FIG. 1
, a clock signal CLK supplied from the outside passes through an input buffer
10
to become an internal first clock signal c-clk. This first clock signal c-clk is supplied to variable delay circuit
11
and variable delay circuit
13
, respectively, and is also supplied to a phase comparator
16
as first clock input. The clock signal inputted to variable delay circuit
13
, after passing through a dummy data output buffer
14
and a dummy input buffer
15
, is supplied as second clock input to the phase comparator
16
. That is, the output of the dummy input buffer
15
is the second clock signal d-i-clk. The phase comparator
16
compares the phases of the first and second clock signals, and outputs the results of comparison to the delay control circuit
17
. The delay control circuit
17
adjusts a delay quantity of variable delay circuit
11
and variable delay circuit
13
on the basis of the phase comparison results. And then, the clock signal c-clk inputted to variable delay circuit
11
, after receiving an adjusted delay quantity in accordance with delay control circuit
17
, is supplied to the data output buffer
12
as a control clock c-clk
1
. The data output buffer
12
, in synchronization with the supplied control clock signal c-clk
1
, captures data DATA, and outputs data output Dout to the outside.
With conventional technology, a delay quantity of a variable delay circuit
11
,
13
is shifted one stage by one stage at a time, until the phase difference between an internal clock signal c-clk synthesized from an external clock signal CLK, and a dummy internal clock signal d-i-clk become, for example, 360 degrees (clock phase match state) and lock on. Because clock cycle fluctuations resulting from changes in power source voltage and ambient temperature are small in the normal active operating state, there are no problems with such a delay quantity single shift system, even when the system shifts in minimum delay units. Rather, since clock cycle fluctuations are small, a single shift system that shifts a delay quantity in minimum delay units is capable of performing phase adjustment in a more stable manner.
However, at operation start when power is turned ON, and at operation restart, which recovers from a standby mode or a power down mode, it takes time to establish a delay quantity required for the DLL circuit to lock on to a variable delay circuit
11
,
13
, which in turn increases the time to the start of actual operations, such as read and write operation, in the memory device, into which this DLL circuit is built.
For example, when power is supplied to the device into which the DLL circuit is built, after resetting a delay quantity of a variable delay circuit
11
,
13
to the initial state, a delay quantity thereof is adjusted. For this reason, the time until the DLL circuit locks on can be longer. In particular, when a delay quantity for locking on is far away from a delay quantity at the above-mentioned reset, a longer time is required until the above-mentioned lock-on is achieved.
Further, when it comes to restarting a DLL circuit-equipped device pursuant to standby mode recovery or power down mode recoverey, since the clock frequency is lowered and/or the power voltage is reduced to cut back on power consumption in the standby mode or the power down mode, a delay quantity of a variable delay circuit
11
,
13
deviates greatly from a delay quantity established in a normal active state. Consequently, the time to DLL circuit lock-on increases in the normal operation start period when recovering from the standby mode or the power down mode.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a DLL circuit, which is capable of shortening the time until lock-on is achieved at DLL circuit normal operation start, or at normal operation restart following recovery from a standby or power down mode.
Another object of the present invention is to provide a DLL circuit, which is capable of shortening the time from a DLL circuit lock-miss state to a lock-on state.
To achieve the above-mentioned objects, the present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock, this DLL circuit comprises: a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phase of the first clock with that of a second clock, which is generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal, wherein the delay control circuit generates a single delay control signal as the delay control signal, which shifts by a minimum delay quantity unit said delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal as the delay control signal, which shifts by a binary unit said delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit.
According to the above-mentioned invention, since phase adjustment is performed in a second operating period in accordance with controlling a delay quantity using a binary shift system, a lock-on state, or a state approximating same can be achieved in a short time, and since phase adjustment is performed in a first operating period in accordance with controlling a delay quantity using a single shift system, stable operation is possible.
In the above-described present invention, according to an embodiment, the delay control circuit comprises a first delay control circuit, which is activated in the above-mentioned first operating period, and which generates the single delay control signal; and a second delay control circuit, which is activated in the above-mentioned second operating period, and which generates the binary delay control signal.
According to the above-described embodiment, by activating the first and second delay control circuits of the delay control circuit in the respective operating periods, it is possible to readily switch between a binary shift system and a single shift system.
Furthermore, in the above-described invention, according to an embodiment the variable delay circuit has a plurality of gates connected in series, and the number of gates through which the first clock passes is variably set in accordance with the delay control signal, and the number of gates inside the variable delay circuit are changed by the minimum delay quantity unit in accordance with a delay control signal generated by the single delay control signal, and the number of gates inside the variable delay circuit are changed in succession to ½ of the total, and thereafter to ¼ or &frac3

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