Divisional operation system for obtaining a quotient by repeated

Details Divisional operation system for obtaining a quotient by repeated Divisional operation system for obtaining a quotient by repeated

1988-03-11

1990-01-02

Malzahn, David H.

Boots, shoes, and leggings

364745, G06F 752

Patent

active

048917800

ABSTRACT:
A divisional operation is performed by the invention, using three registers. The higher order digits or figures of dividend are given to the first register and the lower order digits or figures thereof are given to the second register. In addition, a divisor is given to the third register. Subtraction is performed between the content of the first register and the content of the third register. On the basis of the sign of the result, the quotient is determined. Every time subtraction is performed, a shift operation is conducted in the first and second registers. The quotient is stored in the second register from the least significant bit thereof. In such a shift operation, data of 1 bit is transferred from the most significant bit of the second register to the least significant bit of the first register. Where the data of 1 bit thus transferred represents "1" when the operation is completed, it is detected that division is in an overflow state.

REFERENCES:
patent: 4466077 (1984-08-01), Iannucci et al.
patent: 4692891 (1987-09-01), Yamaoka et al.
Sanyal, "An Algorithm for Non-restoring Division" Computer Design May 1977, pp. 124-127.
Lemaire et al, "Improved Non-Restoring Division", IBM Tech. Disclosure Bulletin, vol. 23, No. 3, Aug. 1980, pp. 1149-1151.
Gerberich et al, "Multiplier/Divider Hardware Design Accelerates Microprocessor Throughput" Computer Design Jun. 1979, pp. 105-112.

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