Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1993-11-30
2001-01-09
Maung, Zarni (Department: 2758)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S620000
Reexamination Certificate
active
06173305
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is the field of digital data processing and more particularly microprocessor circuits, architectures and methods for digital data processing especially digital image/graphics processing.
BACKGROUND OF THE INVENTION
This invention relates to the field of computer graphics and in particular to bit mapped graphics. In bit mapped graphics computer memory stores data for each individual picture element or pixel of an image at memory locations that correspond to the location of that pixel within the image. This image may be an image to be displayed or a captured image to be manipulated, stored, displayed or retransmitted. The field of bit mapped computer graphics has benefited greatly from the lowered cost and increased capacity of dynamic random access memory (DRAM) and the lowered cost and increased processing power of microprocessors. These advantageous changes in the cost and performance of component parts enable larger and more complex computer image systems to be economically feasible.
The field of bit mapped graphics has undergone several stages in evolution of the types of processing used for image data manipulation. Initially a computer system supporting bit mapped graphics employed the system processor for all bit mapped operations. This type of system suffered several drawbacks. First, the computer system processor was not particularly designed for handling bit mapped graphics. Design choices that are very reasonable for general purpose computing are unsuitable for bit mapped graphics systems. Consequently some routine graphics tasks operated slowly. In addition, it was quickly discovered that the processing needed for image manipulation of bit mapped graphics was so loading the computational capacity of the system processor that other operations were also slowed.
The next step in the evolution of bit mapped graphics processing was dedicated hardware graphics controllers. These devices can draw simple figures, such as lines, ellipses and circles, under the control of the system processor. Many of these devices can also do pixel block transfers (PixBlt). A pixel block transfer is a memory move operation of image data from one portion of memory to another. A pixel block transfer is useful for rendering standard image elements, such as alphanumeric characters in a particular type font, within a display by transfer from nondisplayed memory to bit mapped display memory. This function can also be used for tiling by transferring the same small image to the whole of bit mapped display memory. The built-in algorithms for performing some of the most frequently used graphics functions provide a way of improving system performance. However, a useful graphics computer system often requires many functions besides those few that are implemented in such a hardware graphics controller. These additional functions must be implemented in software by the system processor. Typically these hardware graphics controllers allow the system processor only limited access to the bit map memory, thereby limiting the degree to which system software can augment the fixed set of functions of the hardware graphics controller.
The graphics system processor represents yet a further step in the evolution of bit mapped graphics processing. A graphics system processor is a programmable device that has all the attributes of a microprocessor and also includes special functions for bit mapped graphics. The TMS34010 and TMS34020 graphics system processors manufactured by Texas Instruments Incorporated represent this class of devices. These graphics system processors respond to a stored program in the same manner as a microprocessor and include the capability of data manipulation via an arithmetic logic unit, data storage in register files and control of both program flow and external data memory. In addition, these devices include special purpose graphics manipulation hardware that operate under program control. Additional instructions within the instruction set of these graphics system processors controls the special purpose graphics hardware. These instructions and the hardware that supports them are selected to perform base level graphics functions that are useful in many contexts. Thus a graphics system processor can be programmed for many differing graphics applications using algorithms selected for the particular problem. This provides an increase in usefulness similar to that provided by changing from hardware controllers to programmed microprocessors. Because such graphics system processors are programmable devices in the same manner as microprocessors, they can operate as stand alone graphics processors, graphics co-processors slaved to a system processor or tightly coupled graphics controllers.
New applications are driving the desire to provide more powerful graphics functions. Several fields require more cost effective graphics operations to be economically feasible. These include video conferencing, multi-media computing with full motion video, high definition television, color facsimile and digital photography. Each of these fields presents unique problems, but image data compression and decompression are common themes. The amount of transmission bandwidth and the amount of storage capacity required for images and particular full motion video is enormous. Without efficient video compression and decompression that result in acceptable final image quality, these applications will be limited by the costs associated with transmission bandwidth and storage capacity. There is also a need in the art for a single system that can support both image processing functions such as image recognition and graphics functions such as display control.
SUMMARY OF THE INVENTION
This invention is a data processing apparatus for iteratively forming a quotient. The data processing apparatus includes registers for storing various initial and intermediate quantities, a multiplexer selecting data from one of two data registers, a barrel rotator and an arithmetic logic unit. The quotient is formed by trial subtraction.
The multiplexer selects between the data stored in two registers as the source for the next trial subtraction. A first register stores the numerator, which is left shifted each iteration. A second register stores the difference formed by the prior trial subtractions. A status register set by the prior arithmetic logic unit result controls the selection made by the multiplexer. A barrel rotator rotates the data selected by the multiplexer. As previously described, the rotated quantity is stored in the register initially storing the numerator. The arithmetic logic unit subtracts the divisor from the rotated quantity. This difference is stored in the second input register.
The results of the subtraction control the iterative division process. A status register is set based upon whether the difference is less than zero. This status register is used to control the next selection by the multiplexer. If the difference is less than zero, then the rotated data is selected. In that case the quotient bit is “0”. Otherwise, the prior difference is selected and the quotient bit is “1”.
In the preferred embodiment, the numerator is split between two registers. The most significant bits are initially stored in the first register. The least significant bits are initially stored in a multiple flags register. Upon the rotation the most significant from the multiple flags register becomes the least significant bit stored in the first register. The trial difference involves only the most significant bits of the numerator. The arithmetic logic unit forms the difference using the most significant bit shifted out of the multiple flags register, which is supplied to the carry-in input of the arithmetic logic unit. An OR gate receives the most significant bit of the selected data and the carry-out of the arithmetic logic unit. This OR gate supplies the data for the status register and the quotient bit. The quotient bit is stored in the multiple flags register in the lo
Brady III W. James
Marshall, Jr. Robert D.
Maung Zarni
Telecky, Jr. Federick J.
Texas Instruments Incorporated
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