Telecommunications – Receiver or analog modulated signal frequency converter – Frequency modifying or conversion
Reexamination Certificate
2000-01-11
2004-03-16
Vuong, Quochien (Department: 2685)
Telecommunications
Receiver or analog modulated signal frequency converter
Frequency modifying or conversion
C455S131000, C455S205000, C455S260000, C455S313000, C331S016000
Reexamination Certificate
active
06708026
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to frequency synthesizers such as are commonly used in wireless communications mobile terminals and radio frequency receivers, and more particularly to a frequency synthesizer using a digital divider as a local oscillator.
Wireless communications devices, such as cellular telephones and other wireless communications mobile terminals, rely on frequency synthesizers for a wide variety of tasks. For instance, the frequency of the incoming signal is typically mixed with one or more synthesized frequencies to produce lower or “intermediate” frequency signals that may then be further processed by the internal electronics of the device. The synthesized frequencies used for this frequency conversion process must typically be generated within very tight frequency tolerances to properly mix the incoming signals down to the desired intermediate frequencies. Additionally, the synthesized frequencies should have little or no noise associated therewith to avoid corrupting or distorting the signal more than necessary.
Frequency synthesis in wireless communications devices is typically achieved by the use of one or more phase-locked loops. Such phase-locked loops typically include a resonator driven oscillator and comparing/locking circuitry to ensure that the synthesized frequency is at the desired operating frequency. The most common implementation of such a resonator is based on combinations of inductor and capacitor elements, printed transmission line elements on the printed circuit board, dielectric resonators, or Surface Acoustic Wave oscillators. While the quality factors of these resonators are high, and phase noise levels of oscillators built from them are low, the oscillators remain “off chip” components that cannot be integrated together on a single integrated circuit chip. Further, these oscillators may comprise up to fifteen elements which take both up space on the circuit board and add cost.
In recent years, an increased amount of effort has been spent on the integration of low phase noise oscillators into Application Specific Integrated Circuits (ASIC) in order to eliminate the resonator components off the circuit board and to save cost. One goal of such an effort is to develop frequency sources that are fully integrated and have the ability to meet the phase noise specifications levels for today's and tomorrow's wireless and telecommunications applications. However, the results of these development efforts to date have been less than fully satisfactory. As such, there remains a need for an improved method of low phase noise frequency generation that can be incorporated into an ASIC.
BRIEF SUMMARY OF THE INVENTION
The present invention utilizes a programmable digital divider to derive a second synthesized frequency based on a first synthesized frequency. For particular application in the receiver chain of wireless communications mobile terminal, the present invention takes advantage of the fact that the phase noise requirements of the frequency synthesizer for the second mixing stage are relaxed with respect to those of the frequency synthesizer for the first mixing stage. In preferred embodiments, the present invention generates a slightly more noisy synthesized signal, but the majority of the noise is generated away from the centerline frequency and is easily filtered by a commonly available narrowband filter.
In one embodiment, the present invention utilizes a programmable digital divider that operates under the control of a division controller. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division is by an integer amount, but varies between integer values if necessary to achieve a non-integer average division value. In other embodiments, the digital divider is incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for fuller or complete integration onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.
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Klemmer Nikolaus
Montalvo Antonio J.
White Steven L.
Coats & Bennett P.L.L.C.
Ericsson Inc.
Vuong Quochien
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