Dividing circuit calculating a quotient of K m-ary digits in K m

Details Dividing circuit calculating a quotient of K m-ary digits in K m Dividing circuit calculating a quotient of K m-ary digits in K m

1989-10-10

1991-03-19

Shaw, Dale M.

Boots, shoes, and leggings

G06F 738

Patent

active

050016644

ABSTRACT:
For dividing a dividend of a first plurality of m-ary digits by a divisor of a second plurality of m-ary digits to provide a certain number K of m-ary quotient digits, where m represents 2.sup.N, a shift register comprises a most significant part, first and second higher parts for the second plurality less one of m-ary digits and one m-ary digit, and a least significant stage and holds an instantaneous content which is used as a current content during a last part of a preceding one of two consecutive machine cycles and is first a concatenation of an m-ary zero digit and the dividend m-ary digits. A carry save adder tree calculates a set of zeroth to (m-1)-th algebraic sums of a part of the current content held in the most significant and the first and the second higher parts minus zero through (m-1) times the divisor, respectively, plus a carry from a previous machine cycle. The sums are used in deciding a partial quotient of one m-ary digit and a sum datum of the second plurality of m-ary digits. In a leading part of a succeeding one of the consecutive machine cycles, the partial quotient and the sum datum are stored in the least significant stage and the most significant and the first higher parts. After lapse of K machine cycles, the shift register is loaded with an eventual quotient in its stages other than the most significant and the first and the second higher parts.

REFERENCES:
patent: 4635220 (1987-01-01), Yabe et al.
patent: 4707798 (1987-11-01), Nakano
patent: 4725974 (1988-02-01), Kanazawa
patent: 4949295 (1990-08-01), Stearns

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