Dividerless PLL architecture

Details Dividerless PLL architecture Dividerless PLL architecture

2007-07-13

2009-06-16

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C331S017000, C331S025000

Reexamination Certificate

active

07548123

ABSTRACT:
A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.

REFERENCES:
patent: 7068110 (2006-06-01), Frey et al.
patent: 7345549 (2008-03-01), Xu
patent: 2004/0232995 (2004-11-01), Thomsen et al.

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