Divider with cycle time correction

Details Divider with cycle time correction Divider with cycle time correction

2000-08-18

2002-11-26

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S165000, C327S292000, C377S028000, C377S039000

Reexamination Certificate

active

06486717

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a divider with cycle time correction for use as, for example, a timer or a clock signal generator.
2. Description of the Related Art
FIG. 5
shows a prior art circuit consists of a one-chip microcomputer
10
and external circuitry associated with an oscillator.
A CPU
11
in the computer
10
includes a high frequency clock input HCK to which a clock CLK
1
is provided in a normal operating mode, a low frequency clock input LCK to which a clock CLK
2
is provided in a low power consumption mode, and timer interrupt signal inputs INT
1
and INT
2
to which clocks CLK
1
A and CLK
2
A made by dividing frequencies of the clocks CLK
1
and CLK
2
through counters
12
and
22
, respectively, are provided.
The clocks CLK
1
and CLK
2
are of, for example, 4 MHz and 32 kHz, respectively, and generated by oscillators
13
and
23
, respectively.
In the oscillator
13
, a resistor
15
is connected between one input and the output of an NAND gate
14
, and a mode signal MOD
0
from CPU
11
is provided to the other input of the NAND gate
14
. An external crystal oscillator
16
is connected in parallel to the resistor
15
, and external capacitors
17
and
18
are connected between respective ends of the crystal oscillator
16
and a ground line VSS. Constituents
24
to
28
of the oscillator
23
correspond to the constituents
14
to
18
of the oscillator
13
. A mode signal MOD
1
from CPU
11
is provided to one input of an NAND gate
24
.
In the normal operating mode, the mode signals MOD
0
and MOD
1
are set high and low, respectively, and the clock CLK
1
is in operation but the CLK
2
is at rest. In the low power consumption mode, the mode signals MOD
0
and MOD
1
are set low and high, respectively, the clock CLK
1
is at rest and the clock CLK
2
is in operation. Although a timer (an oscillator) constructed of the counter
12
and the oscillator
13
, and a timer constructed of the counter
22
and the oscillator
23
are both of high accuracy, the number of parts, in each timer, are large to cause a cost of the circuit to be high, and the timers cause the number of inputs of the one-chip microcomputer
10
to increase.
FIG. 6
shows another prior art circuit including a one-chip microcomputer
10
A and external circuitry associated with an oscillator.
A CPU
11
A is operable only in the normal operating mode, and a clock CLK
2
A generated by an oscillator
30
is provided to the interrupt signal input INT
2
of the CPU
11
A.
The oscillator
30
includes a Schmitt trigger circuit
31
and an NMOS transistor
32
in the computer
10
A, and a resistor
33
and a capacitor
34
added externally to the computer
10
A. The input and output of the Schmitt trigger circuit
31
are connected to the drain and gate of the NMOS transistor
32
, respectively. The resistor
33
and the capacitor
34
are connected in series between a power supply line VDD and the ground line VSS to constitute a CR integrating circuit. The connection node between the resistor
33
and the capacitor
34
is connected to the input of the Schmitt trigger circuit
31
.
An input signal SW
1
to and an output signal CLK
2
A from the Schmitt trigger circuit
31
are as shown in FIG.
7
. That is, when the potential of the saw tooth wave SW
1
rises to V
1
, the output of the Schmitt trigger circuit
31
goes high to turn the NMOS transistor
32
on, and thereafter the potential of the saw tooth wave SW
1
falls. When the potential of the saw tooth wave SW
1
falls to V
2
, the output of the Schmitt trigger circuit
31
goes low to turn the NMOS transistor
32
off and thereafter, the potential of the SW
1
again rises.
The CPU
11
A accepts an interrupt request on the rising of the clock CLK
2
A and, for example, checks on states of a voltage of a battery for the computer
10
A and a push button (not shown), and executes a processing depending on a result of the checks.
The oscillator
30
of
FIG. 6
has parts in a smaller number than the oscillator constructed of the counter
22
and the oscillator
23
of
FIG. 5
, and costs lower and furthermore, the one-chip microcomputer
10
A has a smaller number of inputs than that of FIG.
5
.
However, since the time constant of the CR integrating circuit varies largely depending on products, the cycle time of the output clock CLK
2
A of the oscillator
30
disperses largely. In order to suppress this disperse, there arises a need to use the resistor
33
and the capacitor
34
, both with high accuracy, thereby increasing a cost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a divider with cycle time correction of high accuracy in spite of employing a low accuracy oscillator.
In one aspect of the present invention, there is provided a divider with cycle time correction comprising: a counter counting a clock and initialized by activation of a first initialization signal; a reference register storing a count of the counter in response to activation of a capture signal; and a comparator activating a coincidence signal to activate the first initialization signal when the count and an output value of the reference register is equal to each other.
With this aspect, even if a clock is generated by a low accuracy oscillator, a coincidence signal whose cycle time is of high accuracy can be obtained as a corrected clock.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 3836858 (1974-09-01), Kitano
patent: 4566111 (1986-01-01), Tanagawa
patent: 5365183 (1994-11-01), Mitshuhira
patent: 5825568 (1998-10-01), Lee
patent: 5982842 (1999-11-01), Ohtsuka et al.
patent: 6046965 (2000-04-01), Oba
patent: 11-17528 (1999-01-01), None

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