Divider synchronization circuit for phase-locked loop frequency

Details Divider synchronization circuit for phase-locked loop frequency Divider synchronization circuit for phase-locked loop frequency

1992-01-31

1994-04-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 16, 331 25, H03L 718

Patent

active

053049519

ABSTRACT:
A divider synchronization circuit (11) that provides faster settling to a new frequency in a phase-locked loop frequency synthesizer (10) that uses a programmable divider (16) and a phase detector (17). The circuit (11) is adapted to stop the divider (16) while its program is being changed, and then restart the divider (16) on command. The startup time of the divider (16) is automatically adjusted such that the divider output is in phase with a reference input to a phase detector (17). The outputs of the phase detector (17) are also blanked during the time period that the divider (16) is stopped. The circuit (11) reduces the time required for the phase locked-loop frequency synthesizer (10) to settle to its new frequency and phase when the frequency is changed. The timing of the divider startup eliminates the large phase transient that may occur when the divider startup timing is random, thus shortening the time that must be allowed for the synthesizer output to settle to its final phase. This circuit (11) is of particular value in a fast settling synthesizer design in which a VCO is pretuned to a close approximation to the new output frequency and then the loop is closed to drive the frequency to its exact value. The circuit (11) is well adapted for use in spread spectrum and frequency-agile radar systems, or spread spectrum communications systems.

REFERENCES:
patent: 4560950 (1985-12-01), Cabot
patent: 4817199 (1989-03-01), Wallraff

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