Divider circuit

Details Divider circuit Divider circuit

2007-03-02

2010-02-02

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S218000

Reexamination Certificate

active

07656204

ABSTRACT:
A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.

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Nikolié, Borivoje, et al. “Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements.”IEEE Journal of Solid-State Circuits. vol. 35, No. 6. IEEE, Jun. 2000. p. 876-884. (10 Pages).
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