Divider and multiplier/divider using said divider

Details Divider and multiplier/divider using said divider Divider and multiplier/divider using said divider

1996-11-14

1998-07-28

Elmore, Reba I.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

057870314

ABSTRACT:
A divider constituted by connecting in series a plurality of arithmetic units in such a manner as to correspond to the number of bits of first data, said divider comprising: a divisor data input unit for inputting a complement of 2 of divisor data in division as said first data signal lines for sending dividend data and said addition result data calculated by said arithmetic unit on the basis of said dividend data and selected by said selector of said arithmetic unit or said carry output data from said arithmetic unit of the most significant bit among said arithmetic units for effecting the arithmetic operation using said second data, as said second data; and an AND circuit for calculating a logical product between a logical product for each bit of said divisor data and said carry output data sent from said signal line, and supplying said logical product as said select signal to said selector.

REFERENCES:
patent: 4441158 (1984-04-01), Kanuma
patent: 5007009 (1991-04-01), Azetsu
patent: 5365471 (1994-11-01), Sato

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