Divided word line type non-volatile semiconductor memory device

Details Divided word line type non-volatile semiconductor memory device Divided word line type non-volatile semiconductor memory device

1990-03-30

1992-07-21

Bowler, Alyssa H.

Static information storage and retrieval

Interconnection arrangements

36523003, 36518901, G11C 700, G11C 800

Patent

active

051329280

ABSTRACT:
An electrically programmable non-volatile semiconductor memory device includes a plurality of internal data transmission lines. Data communication between memory cells and the internal data transmission lines is performed for a byte of data having a plurality of bits. Each of the word lines includes a plurality of divided auxiliary word lines in association with the internal data transmission lines. Those memory cells for each word line that are to be connected to the same internal data transmission line are connected to one auxiliary word line. Only one of a plurality of memory cells connected to one auxiliary word line is connected to an internal data transmission line in operation. Therefore, a plurality of the memory cells connected to different auxiliary word lines, are connected in parallel to a plurality of the internal data transmission lines. According to this arrangement, the effect of word line destruction occasionally caused in one auxiliary word line is not extended to other auxiliary word lines, so that the damaged auxiliary word line can be repaired by the use of an error correction detection code.

REFERENCES:
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patent: 4554646 (1985-11-01), Yoshimoto et al.
patent: 4555778 (1985-11-01), Sakurai
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patent: 4694428 (1987-09-01), Matsumura et al.
patent: 4783767 (1988-11-01), Hamada
patent: 4827449 (1989-05-01), Inoue
patent: 4878203 (1989-10-01), Arakawa
"A 64Kb CMOW EEROM with On-Chip ECC" by S. Mehrotra et al. in IEEE International Solid-State Circuit Conference 1984, Digest of Technical Papers, pp. 142-143.

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