Divided voltage de-coupling structure

Details Divided voltage de-coupling structure Divided voltage de-coupling structure

1998-01-22

2001-08-07

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S311000, C327S320000

Reexamination Certificate

active

06271706

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention generally relates to the field of electronic circuits. More specifically, the present invention relates to de-coupling circuits.
(2) Background Information
De-coupling capacitors are known in the art. Such capacitors may be used for de-coupling high-frequency noise voltages from a load circuit that may receive current from a power source. The noise is typically caused by the load current demand as well as the current source capability of the power supply circuit.
De-coupling of higher voltages may raise particular problems in the case where it is performed on-die by way of devices designed for a low-voltage process. Higher voltages may not be directly applied to on-die devices in a low voltage process because, as the applied voltage is increased, the devices to which the voltage is applied start degrading. In the case where the on-die de-coupling device is a transistor, the respective transistor may be degraded when operated beyond a prescribed range, i.e. when a higher voltage is applied thereto. In a particular instance, the behavior of a transistor in a Complementary Metal Oxide Semiconductor (CMOS) process depends upon the electric field to which the channel of the transistor may be subjected when a certain voltage is applied at the gate of the transistor. If a device such as a transistor is designed for a 3.3 volts process, and one needs to de-couple 4.6 volts, the gate oxide of the transistor operated at 4.6 volts may degrade over time, thus changing the characteristics of the device and consequently influencing the functionality of the device.
Accordingly, it is desirable to provide a reliable on-die de-coupling circuit using devices in a low-voltage process that in combination are able to handle higher voltages. It is desirable that the higher voltages applied to such de-coupling circuits do not cause a degradation of the on-die devices. It is also desirable that the de-coupling circuit consumes very little power.
SUMMARY OF THE INVENTION
In one embodiment the present invention includes an integrated circuit (I.C.) with a de-coupling circuit. The de-coupling circuit includes a voltage divider that includes first and second divider elements. The first and second divider elements are coupled to positive and negative supply voltages, respectively. The first and second divider elements are coupled therebetween at a node. The de-coupling circuit further includes a PMOS transistor and a NMOS transistor that have their gates coupled at the node. The PMOS and NMOS transistors have their sources, drains, and bulks thereof coupled to the positive and negative supply voltages, respectively.


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