Divided drain implant for improved CMOS ESD performance

Details Divided drain implant for improved CMOS ESD performance Divided drain implant for improved CMOS ESD performance

2007-05-15

2007-05-15

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S357000, C257S356000, C257S355000, C257S173000

Reexamination Certificate

active

11156063

ABSTRACT:
A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant structure. The divided drain implant structure further comprises at least two drain implant regions separated by a lightly doped drain region and a halo implant region formed underneath. At least one of the drain implant regions is coupled to an input/output pad of a circuit.

REFERENCES:
patent: 5963409 (1999-10-01), Chang
patent: 6306695 (2001-10-01), Lee et al.
patent: 6329235 (2001-12-01), Kuo
patent: 6878996 (2005-04-01), Rothleitner
patent: 6998685 (2006-02-01), Manna et al.
patent: 7071528 (2006-07-01), Ker et al.

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