Divided clock synchronization

Details Divided clock synchronization Divided clock synchronization

2009-09-25

2011-10-11

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S147000, C327S153000, C327S158000

Reexamination Certificate

active

08035435

ABSTRACT:
Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.

REFERENCES:
patent: 5128940 (1992-07-01), Wakimoto
patent: 5483540 (1996-01-01), Okamura
patent: 6608530 (2003-08-01), Green et al.
patent: 6970115 (2005-11-01), Sardi et al.
patent: 7109756 (2006-09-01), Zhang
Application Note 3901—Synchronizing Multiple High-Speed Multiplexed DACs for Transmit Applications, Maxim Integrated Products, Sep. 21, 2006.

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