Divided clock generation

Details Divided clock generation Divided clock generation

2003-06-13

2004-11-02

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

06812750

ABSTRACT:

BACKGROUND
Most electronic circuits such as microprocessors are synchronous circuits based on clock signals. These clock signals are digital signals which oscillate between a high and a low state such as five volts and zero volts or ground. For example, in a microprocessor operating at 2 gigahertz (gHz), a clock signal in the microprocessor may be oscillating two billion times per second. Various components in the microprocessor use this clock signal to time movement of data or instructions through the microprocessor. For example, one component used extensively in synchronous electronic circuits such as microprocessors is a latch, a component that stores a bit of data. A typical latch has a data input, a clock input, and a data output. When the clock connected to the clock input changes state from low to high, the information (or voltage level) at the data input is copied into the latch and becomes available at the data output, staying in the latch until the clock has oscillated through an entire cycle and again transitions from low to high.
Clock signals, particularly in high speed electronic circuits, are very sensitive signals and are critical to proper operation. Extreme care is taken during the design of the electronic circuit to route the conductors carrying the clock signals properly to minimize interference and to minimize skew, or differences in clock arrival times throughout the circuit. All electrical signals, including clock signals, tend to degrade as they travel over long conductors, so routing of conductors carrying critical clock signals can be a difficult and time-consuming part of the design process. Clock signals are also delayed when they travel across long distances, requiring considerable effort during the design to prevent errors.
Another difficulty when designing synchronous electronic circuits that clock generation circuitry generally requires relatively large analog components, such as phase locked loops (PLLs) which should be isolated from noisy digital circuit regions.
Typical synchronous electronic circuits require multiple clock signals running at various frequencies, such as a core clock and several divided clocks running at various frequencies relative to the core clock. This multiplies the difficulties described above, such as placing multiple analog phase locked loop clock generators and routing multiple clock signal conductors throughout the electronic circuits.
SUMMARY
An exemplary embodiment may comprise an apparatus for generating a divided clock signal, including a buffer circuit having an input and an output, the input being connected to a source clock, the output providing at least one buffered source clock. The apparatus also comprises a plurality of latch chains each having an input and an output, the plurality of latch chains being clocked by the at least one buffered source clock, the plurality of latch chain inputs being connected to a plurality of digital control signals. The apparatus also comprises a combinatorial logic block having a plurality of inputs connected to the plurality of latch chain outputs and to the source clock, and having an output providing a divided clock based on the source clock and aligned with the buffered source clock.
Another exemplary embodiment may comprise a method of generating a clock signal in a remote circuit location, including generating a source clock signal, providing at least one digital control signal for determining a ratio between a frequency of the clock signal and the source clock signal, transmitting the source clock signal and the at least one digital control signal to the remote circuit region in which the clock signal is to be used, and generating the clock signal in the remote circuit location based on the source clock signal and the at least one digital control signal.
Another exemplary embodiment may comprise a clock generation circuit, including means for generating a source clock signal, means for generating a plurality of digital control signals, means for transmitting the source clock signal and the plurality of digital control signals to a remote circuit region where a divided clock is needed, and means for generating the divided clock in the remote circuit region based on the source clock signal and the plurality of digital control signals.


REFERENCES:
patent: 6271702 (2001-08-01), Stansell
patent: 6566918 (2003-05-01), Nguyen

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