Divide-by-two frequency divider

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307279, 307450, 307475, H03K 3289, H03K 3356, H03K 19017, H03K 1920

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active

046238018

ABSTRACT:
An integrated divide-by-two frequency divider circuit in BFL logic of the master-slave flip-flop type which comprises two complementary outputs Q and Q and only a single input for a control signal. The divider is formed only by NOR gates and wired-OR gates. The master does not have a memory function and the various transistors are proportioned so that, .tau..sub.1 being the transit time in the master, .tau..sub.3 the transit time in the first and the second NOR-gate (G.sub.3 and G.sub.4) of the slave, and .tau..sub.4 the transit time in the fourth and the third NOR gate (G.sub.4 and G.sub.5) of the slave, the following inequality is satisfied .tau..sub.1 =1(.tau..sub.3 +.tau..sub.4), thus resulting in a maximum operating frequency which is defined by the relation f.sub.max =1/(.tau..sub.1 +.tau..sub.3 +.tau..sub.4). This circuit is integrated by means of depletion MESFET transistors on a gallium arsenide substrate in a technology including inverter-type gates which are followed by a level translator stage. The invention is used for processing of signals in the gigahertz frequency range of up to 5 GHz.

REFERENCES:
patent: 4450369 (1984-05-01), Scheurmeyer
patent: 4491747 (1985-01-01), Shimizu
patent: 4514649 (1985-04-01), Nuzillat et al.
Cathelin et al, "A 3-5 GHz Self-Aligned Single-Clocked Binary Frequency Divider on GaAs"; IEE Proc., vol. 127, Pt. I, No. 5, pp. 270-277; 10/1980.
Nuzillat et al, "Low Pinch-Off Voltage FET Logic"; IEE Proc, vol. 127, Pt. I, No. 5, pp. 287-296; 10/1980.
Dreyfack, "Gallium Arsenide to Yield 5-GHz Divider"; Electronics; pp. 76 & 78; 10/9/1980.

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