Divide-by-three quadrature frequency divider

Details Divide-by-three quadrature frequency divider Divide-by-three quadrature frequency divider

2008-08-18

2010-11-02

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S115000, C377S047000

Reexamination Certificate

active

07825703

ABSTRACT:
A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

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Oguey et al. “CODYMOS Frequency Dividers Achieve Low Power Consumption and High Frequency”, Electronic Letters, Aug. 23, 1973, pp. 386-387, vol. 9, Issue 17.
Oguey, H.; Vittoz, C.; , “CODYMOS frequency dividers achieve low power consumption and high frequency,” Electronics Letters, vol. 9, No. 17, pp. 386-387, Aug. 23, 1973.

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