Divide by three clock divider with symmetrical output

Details Divide by three clock divider with symmetrical output Divide by three clock divider with symmetrical output

1980-09-25

1982-12-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 41, 307224R, H03K 236, H03K 2106

Patent

active

043663940

ABSTRACT:
A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.

REFERENCES:
patent: 3439278 (1969-04-01), Farrow
patent: 3473129 (1969-10-01), Tschannen
patent: 3571728 (1971-03-01), Andrea et al.
patent: 3902125 (1975-08-01), Oliva
patent: 3943379 (1976-03-01), McGuffin
patent: 4041403 (1977-08-01), Chiapparoli

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